Memory apparatus and methods including merged process for memory cell pillar and source structure

Patent metadata

Field	Value
Publication number	US-12568621-B2
Application number	US-202217726968-A
Country	US
Kind code	B2
Filing date	Apr 22, 2022
Priority date	Apr 22, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the methods includes forming levels of materials one over another; forming a first opening and a second opening in the levels of materials; forming at least one dielectric material in the first and second openings; forming tiers of materials over the levels of materials and over the dielectric material in the first and second openings; forming a first pillar of a memory cell string, the first pillar extending through the tiers of materials and extending partially into a location of the first opening; and forming a second pillar of a contact structure, the second pillar extending through the tiers of materials and through a location of the second opening.

First claim

What is claimed is:

1 . A method comprising:
forming levels of materials one over another; concurrently forming a first opening and a second opening in the levels of materials; forming a dielectric liner in each of the first and second openings; forming at least one material over the dielectric liner in each of the first and second openings; forming tiers of materials over the levels of materials and over the at least one material in the first and second openings; forming an additional opening in the tiers of materials and over the first opening such that a portion of the at least one material in the first opening is exposed at the additional opening; removing at least a portion of the at least one material from the first opening; forming a first pillar of a memory cell string, the first pillar extending through the tiers of materials and extending partially into a location of the first opening; and forming a second pillar of a contact structure, the second pillar extending through the tiers of materials and through a location of the second opening.

2 . The method of claim 1 , wherein at least one material over the dielectric liner includes a dielectric material contacting the dielectric liner.

3 . The method of claim 1 , wherein the first and second openings have different depths in the level of materials.

4 . The method of claim 1 , wherein the levels of materials include:
a level of conductive material; a first level of polysilicon over the level of conductive material; a second level of polysilicon over the first level of polysilicon; a third level of polysilicon over the second level of polysilicon, wherein the first opening is formed such that a portion of the level of conductive material is exposed at the first opening.

5 . The method of claim 4 ,
wherein forming the first opening includes removing a portion of the level of conductive material.

6 . The method of claim 1 , further comprising:
removing a portion of the levels of materials, such that a portion of the dielectric liner in the first opening is exposed at a void where the portion of the levels of materials is removed; removing the portion of the dielectric liner exposed at the void, such that part of a conductive channel portion of the pillar is exposed at the void; and forming a conductive material in the void such that the conductive material is in electrical contact with the conductive channel portion of the pillar and in electrical contact with a remaining portion of the levels of materials.

7 . The method of claim 6 , wherein the material formed in the void includes polysilicon.

8 . The method of claim 1 , wherein the tiers of materials include levels of silicon dioxide to provide separation between control gates for respective memory cells of the memory cell string.

9 . The method of claim 8 , wherein the tiers of materials include levels of silicon nitride interleaved with the levels of silicon dioxide, and the method further comprises:
removing the levels of silicon nitride to form voids at respective locations of the levels of silicon nitride that were removed; and forming control gates in the voids for memory cells of the memory cell string.

10 . A method comprising:
forming levels of materials one over another; forming a first opening and a second opening in the levels of materials; forming a dielectric liner in each of the first and second openings; forming a first material in the first and second openings after forming the dielectric liner; removing the first material in the second opening while keeping the first material in the first opening; forming a second material in the second opening; forming tiers of materials over the levels of materials and over materials in the first and second openings; forming an additional opening in the tiers of materials to expose the first material in the first opening through the additional opening; removing the first material from the first opening; forming a pillar of a memory cell string, the pillar extending through the tiers of material at the additional opening and extending into the first opening; removing a portion of the levels of materials such that a portion of the dielectric liner in the first opening is exposed at a void where the portion of the levels of materials was removed; removing the portion of the dielectric liner exposed at the void, such that part of a conductive channel portion of the pillar is exposed at the void; and forming a conductive material in the void such that the conductive material is in electrical contact with the conductive channel portion of the pillar and in electrical contact with a remaining portion of the levels of materials.

11 . The method of claim 10 , wherein the dielectric liner and the first material have different etch rates.

12 . The method of claim 10 , further comprising:
removing a portion of the first material in the first opening after removing the first material in the second opening and before forming the second material in the second opening, wherein forming the second material in the second opening also forms the second material in the first opening over a remaining portion of the first material in the first opening.

13 . The method of claim 10 , wherein the dielectric liner includes silicon dioxide and the first material is different from silicon dioxide.

14 . The method of claim 10 , wherein the levels of materials include:
a level of conductive material; a first level of polysilicon over the level of conductive material; a second level of polysilicon over the first level of polysilicon; and a third level of polysilicon over the second level of polysilicon, wherein removing the portion of the levels of materials includes removing the second level of polysilicon to expose a portion of the first level of polysilicon and a portion of the third level of polysilicon at the void, wherein the material formed in the void is in electrical contact with the portion of the first level of polysilicon and the portion of the third level of polysilicon.

15 . The method of claim 10 , further comprising:
forming a conductive pillar extending through the tiers of materials and the second opening.

Assignees

• Micron Technology Inc

Inventors

• Kim Byeung Chul
• Wolanyk Joshua
• Hill Richard J
• Fazil Damir

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title