Memory device with cell pads having diagonal sidewalls

Patent metadata

Field	Value
Publication number	US-12568611-B2
Application number	US-202318098202-A
Country	US
Kind code	B2
Filing date	Jan 18, 2023
Priority date	Jan 28, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A semiconductor apparatus includes: a substrate in which a plurality of active areas are provided; a plurality of word lines formed on the substrate and located in a plurality of word line trenches extending in a first direction parallel to a top surface of the substrate; a plurality of bit line structures formed on the substrate, and extending in a second direction parallel to the top surface of the substrate and crossing the first direction; and a plurality of cell pad structures at least partially overlapping the plurality of active areas with the plurality of bit line structures therebetween, wherein each of the plurality of cell pad structures includes a pair of first side walls extending in the first direction and a pair of second side walls extending in a diagonal direction inclined with respect to the first direction and the second direction.

First claim

What is claimed is:

1 . A semiconductor apparatus comprising:
a substrate in which a plurality of active areas are provided; a plurality of word lines formed on the substrate and located in a plurality of word line trenches extending in a first direction parallel to a top surface of the substrate; a plurality of bit line structures formed on the substrate, and extending in a second direction parallel to the top surface of the substrate and crossing the first direction; and a plurality of cell pad structures at least partially overlapping the plurality of active areas with the plurality of bit line structures therebetween, wherein each of the plurality of cell pad structures comprises a pair of first side walls extending in the first direction in a plane defined by the first and second directions and a pair of second side walls extending in a diagonal direction inclined with respect to the first direction and the second direction in the plane.

2 . The semiconductor apparatus of claim 1 , wherein the plurality of cell pad structures comprise a first cell pad and a second cell pad,
wherein each of the first cell pad and the second cell pad has a parallelogram shape.

3 . The semiconductor apparatus of claim 2 , wherein a horizontal cross-sectional area of the first cell pad is a same as a horizontal cross-sectional area of the second cell pad.

4 . The semiconductor apparatus of claim 2 , further comprising:
a plurality of first cell pad separation patterns extending in the first direction on the substrate, and overlapping the pair of first side walls of the plurality of cell pad structures; and a plurality of second cell pad separation patterns extending in the diagonal direction on the substrate, and overlapping the pair of second side walls of the plurality of cell pad structures.

5 . The semiconductor apparatus of claim 4 , wherein the first cell pad, the bit line structure, and the second cell pad are spaced apart from one another, between two adjacent first cell pad separation patterns from among the plurality of first cell pad separation patterns and between two adjacent second cell pad separation patterns from among the plurality of second cell pad separation patterns.

6 . The semiconductor apparatus of claim 4 , further comprising a direct contact located in a direct contact trench extending in the second direction and between the plurality of bit line structures and the plurality of active areas,
wherein the direct contact comprises a pair of first side walls extending in the first direction and a pair of second side walls extending in the second direction.

7 . The semiconductor apparatus of claim 6 , further comprising an insulating fence located in the direct contact trench, and covering at least one second side wall of the pair of second sidewalls of the direct contact and a side wall of the bit line structure,
wherein a bottom surface of the insulating fence is located at a same level as a bottom surface of the direct contact.

8 . The semiconductor apparatus of claim 6 , wherein a bottom surface of the direct contact is located at a level higher than that of bottom surfaces of the first cell pad separation patterns, and
the bottom surface of the direct contact is located at a level higher than bottom surfaces of the second cell pad separation patterns.

9 . The semiconductor apparatus of claim 6 , wherein the direct contact comprises a tail portion protruding outward at a bottom portion of the direct contact.

10 . The semiconductor apparatus of claim 4 , further comprising a direct contact located in a direct contact trench extending in the second direction and between the plurality of bit line structures and the plurality of active areas,
wherein the direct contact comprises a pair of first side walls extending in the diagonal direction and a pair of second side walls extending in the second direction.

11 . The semiconductor apparatus of claim 10 , further comprising an insulating liner located on an inner wall of the direct contact trench,
wherein the insulating liner is located between the pair of first side walls of the direct contact and the pair of second side walls of each of the plurality of the cell pad structures.

12 . A semiconductor apparatus comprising:
a substrate in which a plurality of active areas are provided; a plurality of word lines formed on the substrate and located in a plurality of word line trenches extending in a first direction parallel to a top surface of the substrate; a plurality of bit line structures formed on the substrate, and extending in a second direction parallel to the top surface of the substrate and crossing the first direction; and a plurality of cell pad structures at least partially overlapping the plurality of active areas with the plurality of bit line structures therebetween, wherein each of the plurality of cell pad structures extends in a diagonal direction inclined with respect to the first direction and the second direction in a plane defined by the first and second directions.

13 . The semiconductor apparatus of claim 12 , wherein each of the plurality of cell pad structures comprises a pair of first side walls extending in the first direction, and a pair of second side walls extending in the diagonal direction.

14 . The semiconductor apparatus of claim 13 , wherein each of the plurality of cell pad structures has a parallelogram shape in a plan view.

15 . The semiconductor apparatus of claim 13 , further comprising:
a plurality of first cell pad separation patterns extending in the first direction on the substrate, and overlapping the pair of first side walls of the plurality of cell pad structures; and a plurality of second cell pad separation patterns extending in the diagonal direction on the substrate, and overlapping the pair of second side walls of the plurality of cell pad structures, wherein a first cell pad structure from among the plurality of cell pad structures, the bit line structure, and a second cell pad structure from among the plurality of cell pad structures are spaced apart from one another, between two adjacent first cell pad separation patterns from among the plurality of first cell pad separation patterns and between two adjacent second cell pad separation patterns from among the plurality of second cell pad separation patterns.

16 . The semiconductor apparatus of claim 15 , further comprising a direct contact located in a direct contact trench extending in the diagonal direction and between the plurality of bit line structures and the plurality of active areas,
wherein the direct contact comprises a pair of first side walls extending in the diagonal direction and a pair of second side walls extending in the second direction.

17 . A semiconductor apparatus comprising:
a substrate in which a plurality of active areas are provided; a plurality of word lines formed on the substrate and located in a plurality of word line trenches extending in a first direction parallel to a top surface of the substrate; a plurality of bit line structures formed on the substrate, and extending in a second direction parallel to the top surface of the substrate and crossing the first direction; a plurality of first cell pad separation patterns extending in the first direction on the substrate; a plurality of second cell pad separation patterns extending in a diagonal direction on the substrate, wherein the diagonal direction extends in a plane defined by the first and second directions between the first direction and the second direction; and a pluralit

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Junhyeok

Classifications

• H10B12/485

  Bit line contacts · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title