Dynamic random access memory and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10217748-B2
Application number	US-201715604684-A
Country	US
Kind code	B2
Filing date	May 25, 2017
Priority date	May 25, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) comprising:
a bit line located on a substrate;
a capacitor contact aside the bit line, wherein an upper surface of the capacitor contact is higher than an upper surface of the bit line, such that upper sidewalls of the capacitor contact are exposed by the bit line;
a dielectric structure located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contact, wherein the dielectric structure comprises a first liner layer being partially removed for defining an opening exposing the upper surface of the capacitor contact;
a capacitor located above and electrically contacted to the capacitor contact; and
a landing pad formed in the opening, wherein the landing pad is located between the capacitor contact and the capacitor to electrically connect the capacitor contact and the capacitor together, the landing pad at least covers one portion of the upper surface of the capacitor contact, wherein a contact area between the landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.

2. The DRAM according to claim 1 , wherein the landing pad completely covers the upper surface of the capacitor contact.

3. The DRAM according to claim 2 , wherein the dielectric structure completely covers the upper sidewalls of the capacitor contact.

4. The DRAM according to claim 2 , wherein the landing pad further extends to another portion of the upper sidewalls of the capacitor contact.

5. The DRAM according to claim 1 , wherein the capacitor offsets from the center of the capacitor contact, so that the landing pad only covers one of the upper sidewalls of the capacitor contact.

6. The DRAM according to claim 1 , wherein the number of the bit line is plural, the number of the capacitor contact is plural, and the number of the capacitor is plural, the capacitor contacts are respectively located between the bit lines.

7. The DRAM according to claim 1 , wherein the dielectric structure further comprises a second liner layer over the first liner layer, the first liner layer is conformally formed on the bit line and the capacitor contact and a material of the first liner layer is different from a material of the second liner layer.

8. The DRAM according to claim 7 , wherein the first liner layer comprises silicon oxide, the second liner layer comprises silicon nitride.

9. The DRAM according to claim 1 , wherein an upper surface of the dielectric structure is higher than an upper surface of the landing pad.

10. The DRAM according to claim 1 , wherein a height difference between the upper surface of the capacitor contact and the upper surface of the bit line is 10 nm to 50 nm.

11. The DRAM according to claim 1 , wherein the capacitor contact comprises a first portion and a second portion over the first portion, and a material of the first portion is different from a material of the second portion.

12. The DRAM according to claim 11 , wherein the first portion comprises poly-Si, SiGe, SiC or a combination thereof, the second portion comprises W, TiN, TaN or a combination thereof.

13. A method of manufacturing a dynamic random access memory (DRAM) comprising:
forming a plurality of bit lines on a substrate;
forming a plurality of capacitor contacts respectively between the bit lines, wherein an upper surface of each of the capacitor contacts is higher than an upper surface of each of the bit lines, such that a plurality of recesses are respectively formed on the plurality of the bit lines between the capacitor contacts;
forming a first liner layer on the substrate, wherein the first liner layer conformally covers the upper surfaces of the capacitor contacts and the recesses;
forming a second liner layer on the first liner layer, wherein the recesses are filled with the second liner layer;
forming a dielectric layer on the second liner layer;
forming a plurality of first openings in the first liner layer and forming a plurality of second openings in the dielectric layer and the second liner layer, the second openings respectively located over and connected to the first openings, wherein each of the first openings exposes one portion of the upper surface of a respective capacitor contact and a width of each of the first openings is greater than a width of each of the second openings;
forming a plurality of landing pads in the first openings; and
forming a plurality of capacitors in the second openings, wherein a contact area between each of the landing pads and a respective capacitor contact is greater than a contact area between each of the landing pad and a respective capacitor.

14. The method of manufacturing the DRAM according to claim 13 , wherein steps of forming the first openings and second openings comprises:
performing an etching process to form a plurality of third openings in the dielectric layer, the second liner layer, and the first liner layer, wherein each of the third openings has a uniform width or a taper width; and
performing a widening etching treatment to remove one portion of the first liner layer exposed by the third openings.

15. The method of manufacturing the DRAM according to claim 14 , wherein the etching process comprises a dry etching process, the dry etching process comprises reactive ion etching (RIE) process.

16. The method of manufacturing the DRAM according to claim 14 , wherein the widening etching treatment comprises using an etchant with hydrofluoric acid (HF) and dilute hydrofluoric acid (DHF).

17. The method of manufacturing the DRAM according to claim 13 , wherein the first openings completely expose the upper surfaces of the capacitor contacts.

18. The method of manufacturing the DRAM according to claim 13 , wherein the first openings completely expose the upper surfaces of the capacitor contacts, so that an upper surface of the first liner layer are co-planar with the upper surfaces of the capacitor contacts.

19. The method of manufacturing the DRAM according to claim 13 , wherein the first openings completely expose the upper surfaces of the capacitor contacts and one portion of upper sidewalls of the capacitor contacts, so that an upper surface of the first liner layer are lower than the upper surfaces of the capacitor contacts.

20. The method of manufacturing the DRAM according to claim 13 , wherein each of the second openings is offset from the center of a respective capacitor contact, so that each of the first openings only exposes one of the upper sidewalls of the respective capacitor contact.

Assignees

• Winbond Electronics Corp

Inventors

• Takesako Kazuaki

Classifications

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5283

  Electricity · mapped topic