Semiconductor devices having bit lines and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9865602-B2
Application number	US-201615048075-A
Country	US
Kind code	B2
Filing date	Feb 19, 2016
Priority date	Mar 20, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a bit line provided to cross an active region of a substrate, isolation patterns provided on the substrate to face each other in a direction parallel to the bit line, a storage node contact provided between the isolation patterns to be in contact with a source/drain region provided in an upper portion of the active region, and a spacer provided between the bit line and the storage node contact. Here, the isolation patterns may include a material having an etch selectivity with respect to the spacer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including an active region, an upper portion of the active region comprising a source/drain region:
a bit line on the active region, the bit line crossing the active region and extending longitudinally in a first direction;
a plurality of isolation patterns on a side of the bit line, the plurality of isolation patterns being arranged along the first direction and comprising a first isolation pattern and a second isolation pattern that is adjacent the first isolation pattern;
a storage node contact between the first isolation pattern and the second isolation pattern, the storage node contact contacting the source/drain region; and
a spacer comprising a first spacer and a second spacer secuentially stacked on the side of the bit line and extending between the bit line and the storage node contact and between the bit line and the plurality of isolation patterns,
wherein a first portion of the second spacer that is between the bit line and the storage node contact comprises an uppermost end at a first height from the substrate, a second portion of the second spacer that is between the bit line and the first isolation pattern comprises an uppermost end at a second height from the substrate, and the second height is greater than the first height, and
wherein a first portion of the first spacer that is between the bit line and the storage node contact comprises an uppermost end at a third height from the substrate, and the third height is greater than the first height.

2. The semiconductor device of claim 1 , wherein the first spacer includes a first material different from the second spacer, and
the plurality of isolation patterns include a second material different from the second spacer.

3. The semiconductor device of claim 2 , wherein the spacer further comprises an additional spacer between the first spacer and the second spacer, and
the additional spacer includes a third material different from the plurality of isolation patterns.

4. The semiconductor device of claim 3 , wherein the first spacer includes the same material as the plurality of isolation patterns.

5. The semiconductor device of claim 1 , wherein the spacer further comprises a third spacer, and the first spacer, the second spacer and the third spacer are sequentially stacked on the side of the bit line,
wherein a first portion of the third spacer that is between the bit line and the storage node contact comprises an uppermost end at a fourth height from the substrate, a second portion of the third spacer that is between the bit line and the first isolation pattern comprises an uppermost end at a fifth height from the substrate, and the fifth height is greater than the fourth height, and
wherein the third height is greater than the fourth height.

6. The semiconductor device of claim 5 , wherein the first height is equal to the fourth height.

7. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first spacer is exposed by both the first portion of the second spacer and the storage node contact.

8. The semiconductor device of claim 7 , wherein an upper surface of the storage node contact is at the first height.

9. The semiconductor device of claim 7 , further comprising a landing pad extending along an upper surface of the storage node contact, an upper surface of the first portion of the second spacer, and a surface of the upper portion of the first portion of the first spacer.

10. The semiconductor device of claim 9 , wherein a lower surface of the landing pad contacts the upper surface of the storage node contact, the upper surface of the first portion of the second spacer, and the surface of the upper portion of the first portion of the first spacer.

11. The semiconductor device of claim 10 , wherein a portion of the lower surface of the landing pad that contacts the upper surface of the storage node contact and the upper surface of the first portion of the second spacer has a first width in a second direction that is larger than a second width of the upper surface of the storage node contact in the second direction, and
wherein the second direction perpendicular to the first direction.

12. A semiconductor device comprising:
a substrate including an active region, an upper portion of the active region comprising a source/drain region;
a bit line on the active region, the bit line crossing the active region and extending longitudinally in a first direction;
a plurality of isolation patterns on a side of the bit line, the plurality of isolation patterns being arranged along the first direction and comprising a first isolation pattern and a second isolation pattern that is adjacent the first isolation pattern;
a storage node contact between the first isolation pattern and the second isolation pattern, the storage node contact contacting the source/drain region; and
a spacer between the bit line and the storage node contact, the spacer comprising a first spacer and a second spacer sequentially stacked on the side of the bit line,
wherein both the second spacer and the storage node contact expose an upper portion of the first spacer, and
wherein the second spacer includes a material different from both the first spacer and the plurality of isolation patterns.

13. The semiconductor device of claim 12 , wherein the plurality of isolation patterns include SiBCN, SiCN, SiOCN, or SiN,
wherein the first spacer includes a low k material, SiBCN, SiBN, SiOCN, or SIN, and
wherein the second spacer includes SiN or SiO 2 .

14. The semiconductor device of claim 13 , wherein the first spacer includes a low k material.

15. The semiconductor device of claim 12 , further comprising a landing pad on the storage node contact, wherein the landing pad contacts a side of the upper portion of the first spacer, and
wherein an upper surface of the second spacer is coplanar with an upper surface of the storage node contact.

16. The semiconductor device of claim 12 , wherein the spacer extends in the first direction and extends between the bit line and the plurality of isolation patterns,
wherein a first portion of the second spacer that is between the bit line and the storage node contact comprises an uppermost end at a first height from the substrate, a second portion of the second spacer that is between the bit line and the first isolation pattern comprises an uppermost end at a second height from the substrate, and the second height is greater than the first height.

17. The semiconductor device of claim 1 , wherein a second portion of the first spacer that is between the bit line and the first isolation pattern comprises an uppermost end at the third height.

18. The semiconductor device of claim 17 , wherein the second height is equal to the third height.

19. The semiconductor device of claim 1 , wherein the first spacer includes a low k material, SiBCN, SiBN, SiOCN, or SiN,
wherein the second spacer includes SiN or SiO 2 , and
wherein the plurality of isolation patterns include SiBCN, SiCN, SiOCN, or SIN.

20. The semiconductor device of claim 11 , wherein the storage node contact contacts the first portion of the second spacer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kwon Yongbum

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic