Reference sine generator for PFC controller

Patent metadata

Field	Value
Publication number	US-12567799-B2
Application number	US-202418629746-A
Country	US
Kind code	B2
Filing date	Apr 8, 2024
Priority date	Apr 8, 2024
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A power factor correction (PFC) controller for a PFC switching power supply is disclosed. The PFC controller includes an AC sense terminal, a DC sense terminal, and a reference signal generator coupled to the AC sense terminal. The reference signal generator is configured to receive a divided reference signal generated based on a modified version of an AC input signal and generate a synthesized reference signal using information indicative of an amplitude and a frequency of the divided reference signal. The reference signal generator is further configured to select one of the divided and synthesized reference signals as an output reference signal based on a current amplitude of the divided reference signal. The PFC controller is configured to, based on the output reference signal and a DC voltage sensed on the DC sense terminal, regulate output power provided to a downstream power converter coupled to the PFC switching power supply.

First claim

What is claimed is:

1 . A power factor correction (PFC) controller for a PFC switching power supply, the PFC controller comprising:
an AC sense terminal and a DC sense terminal; a reference signal generator coupled to the AC sense terminal, wherein the reference signal generator is configured to:
receive a divided reference signal generated based on a modified version of an AC input signal;
generate a synthesized reference signal using information indicative of an amplitude and a frequency of the divided reference signal; and
select one of the divided reference signal and the synthesized reference signal as an output reference signal based on a current amplitude of the divided reference signal;
wherein the PFC controller is configured to, based on the output reference signal and a DC voltage sensed on the DC sense terminal, regulate output power provided to a downstream power converter coupled to the PFC switching power supply.

2 . The PFC controller of claim 1 , wherein the PFC controller is configured to control a power factor of the PFC switching power supply based on the output reference signal.

3 . The PFC controller of claim 1 , wherein the reference signal generator includes a synthesizer configured to store a plurality of digital values and further configured to generate the synthesized reference signal using the plurality of digital values.

4 . The PFC controller of claim 3 , wherein the reference signal generator includes a peak detector configured to determine a peak magnitude of the divided reference signal and provide an indication of the peak magnitude to the synthesizer.

5 . The PFC controller of claim 3 , wherein the reference signal generator further includes:
a first comparator configured to generate a first trigger signal based on a comparison of a voltage of the divided reference signal to a first threshold value; a first counter configured to generate a first count value in response to assertion of the first trigger signal, wherein the first count value is indicative of a period of the divided reference signal; a second counter configured to generate a second count value in response to assertion of the first trigger signal; and a second comparator configured to cause the second counter to stop incrementing in response to comparing the voltage of the divided reference signal to a second threshold, wherein the second count value is indicative of a particular time interval.

6 . The PFC controller of claim 5 , wherein the reference signal generator includes a control logic configured to, using the first and second count values, cause the synthesizer to generate and store the plurality of digital values.

7 . The PFC controller of claim 1 , further comprising a multiplexer configured to select the one of the divided reference signal and the synthesized reference signal as the output reference signal.

8 . The PFC controller of claim 7 , wherein the multiplexer is configured to select the divided reference signal as the output reference signal for a first interval that includes a peak amplitude of the AC input signal and further configured to select the synthesized reference signal for a second interval that includes a zero-crossing of the AC input signal.

9 . The PFC controller of claim 7 , wherein the multiplexer is configured to select the synthesized reference signal as the output reference signal after a predetermined number of cycles of the AC input signal.

10 . The PFC controller of claim 7 , wherein the multiplexer is configured to alternate selection of the divided reference signal and the synthesized reference signal during a first interval that includes a peak amplitude of the AC input signal, and further configured to select the synthesized reference signal for a second interval that includes a zero-crossing of the AC input signal.

11 . A method of operating a power factor correction (PFC) switching power supply, the method comprising:
receiving, by a voltage divider, a modified AC signal produced based on an AC input signal; generating, using the voltage divider, a divided reference signal, wherein generating the divided reference signal includes performing a voltage division of the modified AC signal; generating, by a PFC controller and using amplitude and frequency information of the divided reference signal, a synthesized reference signal; selecting, by the PFC controller based on a current amplitude of the divided reference signal, one of the divided reference signal and the synthesized reference signal an output reference signal; and regulating, by the PFC controller and using the output reference signal, output power supplied to a downstream power converter coupled to the PFC switching power supply.

12 . The method of claim 11 , further comprising:
selecting the divided reference signal as the output reference signal for a first interval that includes a peak amplitude of the AC input signal; and selecting the synthesized reference signal for a second interval that includes a zero-crossing of the AC input signal.

13 . The method of claim 11 , further comprising selecting the synthesized reference signal as the output reference signal after a predetermined number of cycles of the AC input signal.

14 . The method of claim 11 , further comprising:
alternating selection of the divided reference signal and the synthesized reference signal during a first interval that includes a peak amplitude of the AC input signal; and selecting the synthesized reference signal for a second interval that includes a zero-crossing of the AC input signal.

15 . The method of claim 11 , further comprising:
storing, in a memory array of a synthesizer, a plurality of digital values; and producing the synthesized reference signal using the plurality of digital values.

16 . The method of claim 15 , wherein generating the plurality of digital values comprises:
comparing, using a first comparator, a voltage of the divided reference signal to a first threshold value; and generating, using a first counter, a first count value in response to the first comparator determining that the voltage of the divided reference signal exceeds the first threshold value, wherein the first count value is indicative of a period of the divided reference signal.

17 . The method of claim 16 , wherein generating the plurality of digital values further comprises:
incrementing, using a second counter, a second count value in response to the first comparator determining that the voltage of the divided reference signal exceeds the first threshold value; comparing, using a second comparator, the voltage of the divided reference signal to a second threshold; and discontinuing incrementing the second counter in response to the voltage of the divided reference signal falling below the second threshold.

18 . The method of claim 17 , further comprising adjusting a phase of the synthesized reference signal with respect to the divided reference signal.

19 . A power factor correction (PFC) switching power supply comprising:
an AC input terminal coupled to receive an AC input signal; a filter configured to reject electromagnetic interference from the AC input signal; a bridge rectifier configured to rectify the AC input signal to produce a rectified AC signal; a switching unit configured to produce a DC output voltage using the rectified AC signal; a voltage divider configured to generate a divided reference signal using a modified version of the AC input signal received by the PFC switching power

Assignees

• Semiconductor Components Ind Llc

Inventors

• Stuler Roman

Classifications

• H02M1/4225 Primary

  using a non-isolated boost converter · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M1/4208 Primary

  Arrangements for improving power factor of AC input · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H03K3/80

  Generating trains of sinusoidal oscillations (by keying or interruption of sinusoidal oscillations H03C; for transmission of digital information H04L) · CPC title