Reference signal generating circuit and method using a sampled input signal and a reference clock signal, and power factor compensation apparatus having the same

Patent metadata

Field	Value
Publication number	US-9537387-B2
Application number	US-201414338765-A
Country	US
Kind code	B2
Filing date	Jul 23, 2014
Priority date	Aug 30, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A reference signal generating circuit is provided that generates a reference signal corresponding to an input signal for power factor compensation of a power converter. The reference signal generating circuit includes a detector sampling the input signal according to a reference clock to detect and hold the maximum input signal and a phase measuring unit measuring a phase of the sampled input signal based on the sampled input signal and the detected maximum input signal. The circuit also includes a reference signal generating unit configured to generate a reference signal having a specific value in response to the measured phase.

First claim

What is claimed is:

1. A reference signal generating circuit for generating a reference signal based on an input signal for power factor compensation of a power converter, the reference signal generating circuit comprising:
a detector configured to sample the input signal according to a reference clock signal and to detect a maximum input signal to hold;
a phase measuring unit configured to measure a phase of the sampled input signal based on the sampled input signal and the detected maximum input signal; and
a reference signal generating unit configured to generate a reference signal having a specific value in response to the measured phase, wherein the reference signal generating unit is configured to sample and to hold the generated reference voltage based on the reference clock signal to output the reference signal.

2. The reference signal generating circuit of claim 1 , wherein the detector comprises:
a sampling unit configured to repeatedly sample the input signal and hold the sampled input signal based on the reference clock signal; and
a peak detector configured to detect and hold the maximum input signal.

3. The reference signal generating circuit of claim 1 , wherein the phase measuring unit comprises a selection switch configured to alternately couple the sampling unit and an output terminal of the detector to an input terminal of the phase measuring unit based on the reference clock signal.

4. The reference signal generating circuit of claim 1 , wherein the phase measuring unit comprises:
a calculation unit configured to alternately receive and integrate the sampled input signal according to the reference clock signal and the detected maximum input signal to generate an intermediate calculation signal; and
a calculation control unit configured to convert the intermediate calculation signal into a time domain to measure the phase of the sampled input signal.

5. The reference signal generating circuit of claim 4 , wherein the calculation unit performs a positive integration calculation on the sampled input signal and performs a negative integration calculation on the detected maximum input signal.

6. The reference signal generating circuit of claim 4 , wherein the calculation control unit generates a pulse signal based on an interval where a level of the intermediate calculation signal is larger than a reference value while the calculation unit performs the integral calculation on the detected maximum input signal.

7. The reference signal generating circuit of claim 1 , wherein the phase measuring unit comprises a division calculation unit configured to measure a phase of the sampled input signal by performing a division calculation.

8. The reference signal generating circuit of claim 1 , wherein the reference signal generating unit comprises:
a current source configured to provide a current having a specific value;
a capacitor configured to charge using the current having the specific value to generate a reference voltage; and
a switch configured to serially couple the current source and the capacitor based on the measured phase.

9. A power factor compensation apparatus for compensating a power factor of a power converter, the power factor compensation apparatus comprising:
a power transfer device into which an input current corresponding to an input signal flows;
an output switch that is coupled to the power transfer device, the output switch being configured to adjust an output voltage that is generated by the input current of the power transfer device;
an output capacitor configured to charge using the input current to generate a output voltage;
a reference signal generating circuit configured to generate a reference signal based on the input signal; and
a power factor compensation control unit configured to compare the output voltage and the reference signal to control the output switch,
wherein the reference signal generating circuit comprises
a detector configured to sample the input signal according to a reference clock signal and to detect a maximum input signal to hold,
a phase measuring unit configured to measure a phase of the sampled input signal based on the sampled input signal and the detected maximum input signal, and
a reference signal generating unit configured to generate a reference signal having a specific value in response to the measured phase, wherein the phase measuring unit comprises
a calculation unit configured to alternately receive and integrate the sampled input signal according to the reference clock signal and the detected maximum input signal to generate an intermediate calculation signal.

10. A reference signal generating method for generating a reference signal corresponding to an input signal for a power factor compensation of a power converter, the reference signal generating method comprising:
sampling the input signal based on a reference clock and detecting a maximum input signal to hold;
measuring a phase of the sampled input signal based on the sampled input signal and the detected maximum input signal; and
generating a reference signal having a specific value in response to the measured phase, wherein the measuring comprises
alternately receiving and integrating the sampled input signal according to the reference clock signal and the detected maximum input signal to generate an intermediate calculation signal.

11. The reference signal generating method of claim 10 , wherein the measuring comprises alternately selecting the sampled input signal based on the reference clock signal and the detected maximum input signal.

12. The reference signal generating method of claim 11 , wherein the measuring further comprises:
converting the intermediate calculation signal into a time domain to measure the phase of the sampled input signal.

13. The reference signal generating method of claim 12 , wherein the converting generates a pulse signal based on an interval where a level of the intermediate calculation signal is larger than a reference value while the integration calculation for the detected maximum input signal is performed.

14. The reference signal generating method of claim 10 , wherein the alternatively receiving and integrating comprises performing a positive integration calculation on the sampled input signal and performing a negative integration calculation on the detected maximum input signal.

15. The reference signal generating method of claim 10 , wherein the generating the reference signal charges a capacitor using a current having a specific value based on the measured phase to generate a reference voltage.

16. The reference signal generating method of claim 15 , wherein the generating the reference signal further comprises sampling and holding the generated reference voltage based on the reference clock signal to output the reference signal.

17. The reference signal generating method of claim 10 , wherein the measuring measures a phase of the sampled input signal by performing a division calculation.

18. The apparatus of claim 9 , wherein the phase measuring unit further comprises a calculation control unit configured to convert the intermediate calculation signal into a time domain to measure the phase of the sampled input signal.

19. A circuit for measuring phase information, the circuit comprising:
a detector configured to sample the input signal according to a reference clock signal and to detect a maximum input signal to hold; and
a phase measuring unit configured to measure a phase of the sampled input signal based on the sampled input signal

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Cui zhi yuan
• Ryu Younggi
• Hwang Inho
• Jung Sang Hoon
• Park Taeyoung

Classifications

• H02M1/42

  Circuits or arrangements for compensating for or adjusting power factor in converters or inverters · CPC title

• H02M1/4208

  Arrangements for improving power factor of AC input · CPC title

• Y02B70/126

  Cross-Sectional Technologies · mapped topic

• H02M2001/0025

  Electricity · mapped topic

• G01R25/005 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title