Electronic device having stacked-patch antenna with floating ground via

US12567673B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12567673-B2
Application numberUS-202318477868-A
CountryUS
Kind codeB2
Filing dateSep 29, 2023
Priority dateSep 29, 2023
Publication dateMar 3, 2026
Grant dateMar 3, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device may be provided with an antenna module having a substrate. An antenna may be disposed on the substrate. The antenna may have a directly fed patch and parasitic patches. The antenna may be fed by a feed via. The parasitic patches may include a first layer of parasitic patches separated by a gap overlapping the directly fed patch. The parasitic patches may include an additional parasitic patch formed in a second layer. The additional parasitic patch may overlap the gap. A floating ground via may couple a center of the additional parasitic patch and a center of the directly fed patch to a landing pad in a ground layer. The landing pad may short the via to the ground layer at the radiating frequency of the antenna. The landing pad may be electrically floating at DC frequencies.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic device comprising: a substrate having a first, second, and third metallization layers, the second metallization layer being interposed between the first and third metallization layers; ground traces in the first metallization layer; an antenna having a directly fed patch in the second metallization layer and a parasitic patch in the third metallization layer, wherein the directly fed patch overlaps the ground traces, the parasitic patch overlaps the directly fed patch, and the antenna is configured to radiate at a frequency; a hole in the ground traces; a landing pad in the first metallization layer and disposed in the hole; and a conductive via that couples the parasitic patch and the directly fed patch to the landing pad, wherein the landing pad and the conductive via are configured to electrically short the directly fed patch and the parasitic patch to the ground traces at the frequency. 2 . The electronic device of claim 1 , wherein the landing pad is electrically floating with respect to the ground traces at an additional frequency lower than the frequency. 3 . The electronic device of claim 2 , wherein the frequency is greater than 10 GHz and the additional frequency is a direct current (DC) frequency. 4 . The electronic device of claim 1 , wherein the conductive via extends along a central axis of the parasitic patch and the directly fed patch. 5 . The electronic device of claim 4 , wherein the conductive via is coupled to a center of the directly fed patch and is coupled to a center of the parasitic patch. 6 . The electronic device of claim 5 , further comprising: a feed via coupled to the directly fed patch along an edge of the directly fed patch. 7 . The electronic device of claim 6 , further comprising: a fourth metallization layer on the substrate, the first metallization layer being interposed between the fourth and second metallization layers; and a transmission line having a signal trace formed from the fourth metallization layer, wherein the feed via couples the signal trace to the directly fed patch through an opening in the ground traces. 8 . The electronic device of claim 7 , further comprising: an additional transmission line having an additional signal trace formed from the fourth metallization layer; and an additional feed via that couples the additional signal trace to the directly fed patch along an additional edge of the directly fed patch that is orthogonal to the edge of the directly fed patch. 9 . The electronic device of claim 1 , further comprising: a fourth metallization layer on the substrate, the fourth metallization layer being interposed between the second and third metallization layers, wherein the antenna has a set of additional parasitic patches that are formed from the fourth metallization layer and that at least partially overlap the directly fed patch. 10 . The electronic device of claim 9 , the set of additional parasitic patches comprising a first additional parasitic patch and a second additional parasitic patch separated from the first additional parasitic patch by a gap, wherein the parasitic patch overlaps the gap and the conductive via extends from the directly fed patch to the parasitic patch through the gap. 11 . The electronic device of claim 10 , wherein the conductive via is coupled to a center of the parasitic patch and a center of the directly fed patch. 12 . An antenna module comprising: a substrate having antenna layers and transmission line layers; ground traces that separate the antenna layers from the transmission line layers; a signal trace in the transmission line layers; an antenna having a first patch overlapping the ground traces and a second patch overlapping the first patch; a first conductive via that couples the signal trace to the first patch through the transmission line layers, a first hole in the ground traces, and the antenna layers; a landing pad disposed in a second hole in the ground traces, wherein the landing pad is electrically floating at a direct current (DC) frequency; and a second conductive via that couples the first patch and the second patch to the landing pad. 13 . The antenna module of claim 12 , wherein the landing pad is configured to electrically short the second conductive via to the ground traces at a radiating frequency of the antenna. 14 . The antenna module of claim 13 , wherein the radiating frequency is greater than 10 GHz. 15 . The antenna module of claim 12 , wherein the second conductive via is coupled to a center of the first patch. 16 . The antenna module of claim 15 , wherein the second conductive via is coupled to a center of the second patch. 17 . The antenna module of claim 12 , further comprising: first, second, third, and fourth parasitic patches at least partially overlapping the first patch and being separated from the first patch by a first distance, wherein the second patch comprises a fifth parasitic patch separated from the first patch by a second distance greater than the first distance. 18 . The antenna module of claim 17 , wherein the first parasitic patch is laterally separated from the second parasitic patch by a gap, the third parasitic patch is laterally separated from the fourth parasitic patch by the gap, the fifth parasitic patch overlaps the gap, and the second conductive via extends through the gap. 19 . An antenna comprising: a ground layer; a patch overlapping the ground layer; an antenna feed terminal coupled to the patch; first and second parasitic patches overlapping the patch, the first and second parasitic patches being separated by a gap; a third parasitic patch overlapping the gap; and a floating ground via that is coupled to the patch and the third parasitic patch and that extends through the gap. 20 . The antenna of claim 19 , wherein the floating ground via is coupled to a landing pad disposed in a hole in the ground layer, wherein the landing pad exhibits a short circuit impedance to the ground layer at a radiating frequency of the antenna and exhibits an open circuit impedance to the ground layer at a direct current (DC) frequency.

Assignees

Inventors

Classifications

  • in a stacked or folded configuration · CPC title

  • Patch antenna using one or more coplanar parasitic elements · CPC title

  • H01Q9/045Primary

    with particular feeding means (for circular polarisation H01Q9/0428) · CPC title

  • H01Q1/243Primary

    with built-in antennas · CPC title

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Frequently asked questions

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What does patent US12567673B2 cover?
An electronic device may be provided with an antenna module having a substrate. An antenna may be disposed on the substrate. The antenna may have a directly fed patch and parasitic patches. The antenna may be fed by a feed via. The parasitic patches may include a first layer of parasitic patches separated by a gap overlapping the directly fed patch. The parasitic patches may include an addition…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification H01Q9/045. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).