Method of forming structures including a vanadium or indium layer

Patent metadata

Field	Value
Publication number	US-12563983-B2
Application number	US-202217989081-A
Country	US
Kind code	B2
Filing date	Nov 17, 2022
Priority date	Feb 3, 2020
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and/or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

First claim

What is claimed is:

1 . A semiconductor device structure, comprising:
a substrate; a vanadium layer comprising vanadium and at least one of oxygen, nitrogen, sulfur, and carbon disposed on a surface of the substrate; and an insulating material disposed on the surface of the substrate between the substrate and the vanadium layer, wherein the insulating material comprises an interface layer disposed directly on the surface of the substrate and a high-k dielectric layer overlying the interface layer, wherein the interface layer comprises silicon oxide and the high-k dielectric layer comprises one or more of hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium silicate (HfSiO x ), aluminum oxide (Al 2 O 3 ), and lanthanum oxide (La 2 O 3 ).

2 . The semiconductor device structure of claim 1 , further comprising a conducting layer disposed on top of the vanadium layer, wherein the conducting layer comprises at least one of titanium nitride, vanadium nitride, titanium aluminum carbon, tungsten, tungsten carbon nitride, cobalt, copper, molybdenum, and ruthenium.

3 . The semiconductor device structure of claim 1 , wherein the vanadium layer comprises a binary compound comprising vanadium and one of oxygen, nitrogen, sulfur, and carbon.

4 . The semiconductor device structure of claim 1 , wherein the vanadium layer comprises a ternary compound comprising vanadium and two of oxygen, nitrogen, sulfur, and carbon.

5 . The semiconductor device structure of claim 1 , wherein the vanadium layer comprises a vanadium compound represented by a chemical formula of M x X y Z a , where Mis vanadium, X is one of oxygen, nitrogen, sulfur, and carbon, Z is one of oxygen, nitrogen, sulfur, and carbon, and wherein x is greater than 0 and less than one, and y ranges from 0 to less than 1, and a ranges from 0 to less than 1.

6 . The semiconductor device structure of claim 1 , wherein the vanadium layer comprises at least one of vanadium nitride and vanadium carbon nitride.

7 . The semiconductor device structure of claim 6 , wherein the vanadium layer comprises about 4 at % to about 8 at % carbon.

8 . The semiconductor device structure of claim 1 , wherein the vanadium layer comprises impurities in an amount of less than one atomic percent.

9 . A semiconductor device structure formed by performing the steps of:
providing a substrate within a reaction chamber of a reactor; using a cyclical deposition process, depositing a layer comprising one or more of vanadium and indium onto an insulating material disposed on a surface of the substrate, wherein the insulating material comprises an interface layer disposed directly on the surface of the substrate and a high-k dielectric layer overlying the interface layer, and wherein the interface layer comprises silicon oxide and the high-k dielectric layer comprises one or more of hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium silicate (HfSiO x ), aluminum oxide (Al 2 O 3 ), and lanthanum oxide (La 2 O 3 ), wherein the cyclical deposition process comprises:
continually flowing one or more of a vanadium precursor and an indium precursor to the reaction chamber; and
while continually flowing the one or more of the vanadium precursor and the indium precursor, periodically pulsing one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant to the reaction chamber.

Assignees

• Asm Ip Holding Bv

Inventors

• Shero Eric James
• Givens Michael Eugene
• Xie Qi
• Dezelah Charles
• Alessio Verni Giuseppe

Classifications

• C23C16/45553

  characterized by the use of precursors specially adapted for ALD · CPC title

• C23C16/18

  from metallo-organic compounds · CPC title

• C23C16/06

  characterised by the deposition of metallic material · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title