Display substrate and display device being capable of reducing the load of signal lines

Patent metadata

Field	Value
Publication number	US-12563930-B2
Application number	US-202017611795-A
Country	US
Kind code	B2
Filing date	Mar 25, 2020
Priority date	Mar 25, 2020
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Disclosed are a display substrate and a display device. The display substrate includes: a base substrate, a first gate layer, a second gate layer and a first conductive layer. The first gate layer includes a reset signal line extending in a first direction, and a first electrode block; the second gate layer includes a second electrode block, wherein the second electrode block is configured to form a storage capacitor with the first electrode block; and the first conductive layer includes a power line extending in a second direction, wherein the reset signal line and the power line have a first overlapped region, and the second electrode block and the power line have a second overlapped region. The width of the power line located in the first overlapped region is smaller than the width of the power line located in the second overlapped region.

First claim

The invention claimed is:

1 . A display substrate, comprising:
a base substrate; a first gate electrode layer on the base substrate; a second gate electrode layer at a side of the first gate electrode layer away from the base substrate; and a first conductive layer at a side of the second gate electrode layer away from the base substrate, wherein the first gate electrode layer comprises a reset signal line extending along a first direction and a first electrode block, the second gate electrode layer comprises a second electrode block, the second electrode block is configured to form a storage capacitor with the first electrode block, the first conductive layer comprises a power line extending along a second direction, the reset signal line has a first overlapping region with the power line, and the second electrode block has a second overlapping region with the power line, a width of the power line in the first overlapping region is less than a width of the power line in the second overlapping region, and the first direction intersects with the second direction, the display substrate further comprises a semiconductor layer at a side of the first gate electrode layer close to the base substrate, the semiconductor layer comprises a first unit, a second unit, and a third unit, the first unit comprises a first channel region, and a first source electrode region and a first drain electrode region located at two sides of the first channel region, the third unit comprises two third channel regions, a common electrode between the two third channel regions, and a third source electrode region and a third drain electrode region located at two sides of the two third channel regions, the first electrode block is overlapped with the first channel region of the first unit and serves as a gate electrode of the first unit, the third source electrode region is connected with the first drain electrode region, and the third drain electrode region is connected with the gate electrode of the first unit, the second gate electrode layer further comprises a conductive block and an initialization signal line extending along the first direction, the conductive block is configured to receive a driving voltage, an orthographic projection of the conductive block on the base substrate is spaced apart from an orthographic projection of the initialization signal line on the base substrate, an orthographic projection of the conductive block on the base substrate is overlapped with an orthographic projection of the common electrode on the base substrate, and the power line comprises a block overlapping region with the conductive block, and an average width of the power line in the block overlapping region is smaller than the width of the power line in the second overlapping region.

2 . The display substrate according to claim 1 , wherein the width of the power line in the first overlapping region is less than an average width of the power line.

3 . The display substrate according to claim 1 , wherein the power line comprises a body extending portion and a narrowing portion, a width of the narrowing portion is less than a width of the body extending portion, and an orthographic projection of the narrowing portion on the base substrate overlaps with an orthographic projection of the reset signal line on the base substrate.

4 . The display substrate according to claim 1 , wherein the first gate electrode layer further comprises a gate line extending along the first direction, and the gate line and the power line have a third overlapping region, and a width of the power line in the third overlapping region is less than a width of the power line in the second overlapping region.

5 . The display substrate according to claim 4 , wherein a width of the power line in the first overlapping region is less than an average width of the power line.

6 . The display substrate according to claim 4 , wherein the power line comprises a body extending portion and a narrowing portion, a width of the narrowing portion is less than a width of the body extending portion, and an orthographic projection of the narrowing portion on the base substrate overlaps with an orthographic projection of the gate line on the base substrate.

7 . The display substrate according to claim 1 , wherein a width of the reset signal line in the fourth overlapping region is less than ¾ of a maximum width of the reset signal line.

8 . The display substrate according to claim 1 , wherein the data line and the initialization signal line have a fifth overlapping region, and the initialization signal line and the semiconductor layer have a sixth overlapping region,
a width of the initialization signal line in the fifth overlapping region is less than a width of the initialization signal line in the sixth overlapping region.

9 . The display substrate according to claim 8 , wherein the width of the initialization signal line in the fifth overlapping region is less than an average width of the initialization signal line.

10 . The display substrate according to claim 8 , wherein the power line comprises a body extending portion and a narrowing portion, a width of the narrowing portion is less than a width of the body extending portion, and an orthographic projection of the narrowing portion on the base substrate does not overlap with an orthographic projection of the semiconductor layer on the base substrate.

11 . The display substrate according to claim 10 , wherein the body extending portion comprises a connection portion connected with the conductive block, an orthographic projection of the connection portion on the base substrate overlaps with an orthographic projection of the semiconductor layer on the base substrate, and the connection portion is adjacent to the narrowing portion in the second direction.

12 . The display substrate according to claim 8 , wherein the semiconductor layer further comprises a fourth unit, a fifth unit, a sixth unit and a seventh unit,
the second unit comprises a second channel region, and a second source electrode region and a second drain electrode region located at two sides of the second channel region, the fourth unit comprises a fourth channel region, and a fourth source electrode region and a fourth drain electrode region located at two sides of the fourth channel region, the fifth unit comprises a fifth channel region, and a fifth source electrode region and a fifth drain electrode region located at two sides of the fifth channel region, the sixth unit comprises a sixth channel region, and a sixth source electrode region and a sixth drain electrode region located at two sides of the sixth channel region, the seventh unit comprises a seventh channel region, and a seventh source electrode region and a seventh drain electrode region located at two sides of the seventh channel region.

13 . The display substrate according to claim 12 , wherein the sixth drain electrode region is connected to the third drain electrode region, the third source electrode region, the first drain electrode region and the fifth source electrode region are connected to a first node, the first source electrode region, the second drain electrode region and the fourth drain electrode region are connected to a second node, and the fifth drain electrode region is connected to the seventh drain electrode region.

14 . The display substrate according to claim 13 , wherein the sixth source electrode region and the seventh source electrode region are connected to the initialization signal line.

15 . The display substrate according to claim 13 , wherein the second source el

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yang Lulu
• Shang Tinghua
• Qu Yi
• Zhang Xin
• Li Huijun
• Jiang Xiaofeng
• Wang Mengqi
• Zhang Meng
• Wang Siyu

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title