Electronic devices comprising a stack structure, a source contact, and a dielectric material

Patent metadata

Field	Value
Publication number	US-12563787-B2
Application number	US-202418421820-A
Country	US
Kind code	B2
Filing date	Jan 24, 2024
Priority date	Jan 26, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.

First claim

What is claimed is:

1 . An electronic device, comprising:
a source contact between a source stack and a dielectric material, the dielectric material comprising a doped dielectric material or a high-k dielectric material; and memory pillars extending through tiers adjacent to the dielectric material and into the source stack, the source contact directly contacting a channel of the memory pillars, the channel extending continuously along a height of the memory pillars and one or more of a tunnel dielectric material, a charge trap material, and a charge blocking material extending along a portion of the height of the memory pillars.

2 . The electronic device of claim 1 , wherein the doped dielectric material or the high-k dielectric material is formulated to be selectively etchable relative to one or more materials of the memory pillars.

3 . The electronic device of claim 1 , wherein a portion of the tunnel dielectric material, the charge trap material, and the charge blocking material of the memory pillars is above the source contact and an additional portion of the tunnel dielectric material, the charge trap material, and the charge blocking material of the memory pillars is below the source contact.

4 . The electronic device of claim 3 , wherein a lower surface of the charge trap material above the source contact is recessed relative to a lower surface of the tunnel dielectric material above the source contact.

5 . The electronic device of claim 1 , wherein the channel of the memory pillars extends through the source contact.

6 . An electronic device, comprising:
a doped dielectric material or a high-k dielectric material between a source contact and tiers, the source contact overlying a source stack; and memory pillars extending from the tiers to the source stack, a length of a charge blocking material of the memory pillars being relatively shorter than a length of one or more additional materials of the memory pillars.

7 . The electronic device of claim 6 , wherein the length of the charge blocking material is less than a length of a charge trap material of the memory pillars.

8 . The electronic device of claim 6 , wherein a length of a charge trap material of the memory pillars is greater than a length of one or more of a tunnel dielectric material and a charge blocking material of the memory pillars.

9 . The electronic device of claim 6 , wherein a width of the source contact vertically adjacent to the charge blocking material is greater than a width of the source contact vertically adjacent to the doped dielectric material or the high-k dielectric material.

10 . The electronic device of claim 6 , wherein the tiers comprise alternating conductive materials and dielectric materials and one or more tiers proximal to the doped dielectric material or the high-k dielectric material is configured as a select gate source.

11 . An electronic device, comprising:
a dielectric material between a source contact and tiers overlying a source stack; and memory pillars comprising a channel, a tunnel dielectric material, a charge trap material, and a charge blocking material in an active region of the electronic device, the memory pillars extending through the tiers and into the source stack, the source contact extending horizontally over the source stack and directly contacting the channel of the memory pillars, the channel extending continuously along the memory pillars, a portion of one or more of the tunnel dielectric material, the charge trap material, and the charge blocking material above the source contact, and an additional portion of the one or more of the tunnel dielectric material, the charge trap material, and the charge blocking material below the source contact.

12 . The electronic device of claim 11 , wherein the portion of the one or more of the tunnel dielectric material, the charge trap material, and the charge blocking material above the source contact and the additional portion of the one or more of the tunnel dielectric material, the charge trap material, and the charge blocking material below the source contact are separated by the source contact.

13 . The electronic device of claim 11 , wherein the dielectric material between the source contact and the tiers comprises a doped dielectric material or a high-k dielectric material.

14 . The electronic device of claim 11 , wherein the dielectric material between the source contact and the tiers comprises a high-k oxide material, a high-k metal oxide material, or a combination thereof.

15 . The electronic device of claim 11 , wherein the dielectric material between the source contact and the tiers comprises doped silicon nitride or doped silicon oxide.

16 . The electronic device of claim 15 , wherein the dielectric material comprises carbon doped silicon nitride, carbon doped silicon oxide, boron doped silicon nitride, or boron doped silicon oxide.

17 . The electronic device of claim 11 , further comprising a source contact sacrificial structure in peripheral regions of the electronic device.

18 . The electronic device of claim 17 , wherein the source contact sacrificial structure is between the dielectric material and the source stack.

19 . The electronic device of claim 17 , wherein the source contact sacrificial structure in the peripheral regions and the source contact in the active region exhibit a same thickness.

20 . The electronic device of claim 11 , wherein the channel comprises polysilicon and the source contact comprises doped polysilicon.

Assignees

• Micron Technology Inc

Inventors

• Lindemann Michael A
• Howder Collin
• Fukuzumi Yoshiaki
• Hill Richard J

Classifications

• H10D64/251

  Source or drain electrodes for field-effect devices · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/6743

  Silicon · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title