Memory devices and systems having reduced bit line to drain select gate shorting and associated methods

Patent metadata

Field	Value
Publication number	US-10134758-B2
Application number	US-201715683672-A
Country	US
Kind code	B2
Filing date	Aug 22, 2017
Priority date	Dec 15, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

First claim

What is claimed is:

1. A method of forming a memory structure, comprising:
providing a layered semiconductor substrate having a contact region, a source select gate (SGS) layer on the contact region, and a tiered stack of semiconductor layers on the SGS layer;
forming a drain select gate (SGD) layer on the tiered stack of the semiconductor substrate;
forming one or more insulating layers on the SGD layer;
etching a pillar trench from the one or more insulating layers into the contact region of the semiconductor substrate;
forming a central pillar in the pillar trench from the contact region into the one or more insulating layers;
forming a plug recess by etching sidewalls of the one or more insulating layers around the pillar trench and a portion of the central pillar;
forming a T-plug in the plug recess; and
forming an electrical contact on the T-plug such that the T-plug provides a barrier against electrical shorting from the electrical contact to the SGD layer.

2. The method of claim 1 , wherein the one or more insulating layers comprises two insulating layers.

3. The method of claim 2 , wherein the two insulating layers include an oxide isolating layer and a nitride isolating layer.

4. The method of claim 1 , wherein forming the central pillar in the pillar trench extends from within the contact region onto a top surface of the one or more insulating layers.

5. The method of claim 4 , wherein forming the plug recess further comprises etching central pillar material from the top surface of the one or more insulating layers.

6. The method of claim 1 , wherein forming the T-plug further comprises:
forming the T-plug in the plug recess and across a top surface of the one or more insulating layers; and
removing a portion of the T-plug to expose the top surface of the one or more insulating layers.

7. The method of claim 1 , further comprising forming an insulating top layer across the T-plug and the one or more insulating layers.

8. The method of claim 7 , wherein forming the electrical contact further comprises forming the electrical contact on the T-plug through the insulating top layer.

9. The method of claim 1 , wherein the semiconductor substrate further comprises an array of charge storage devices within the tiered stack of semiconductor layers oriented along the central pillar.

10. The method of claim 1 , wherein the central pillar is p-type and the T-plug is n-type.

11. The method of claim 1 , wherein the central pillar and the T-plug comprise polysilicon.

12. The method of claim 3 , wherein the nitride isolation layer is formed on the SDG layer.

13. The method of claim 1 , wherein the oxide isolation layer is formed on the nitride isolation layer.

14. The method of claim 13 , wherein the pillar trench is etched from the oxide isolation layer into the contact region of the semiconductor substrate.

15. The method of claim 13 , wherein forming the central pillar in the pillar trench extends from within the contact region at least to the top surface of the nitride isolation layer.

16. The method of claim 13 , wherein forming the central pillar in the pillar trench extends from within the contact region at least into the oxide isolation layer.

17. The method of claim 14 , wherein forming the plug recess further comprises etching central pillar material from the top surface of the oxide isolation layer.

18. The method of claim 13 , wherein etching sidewalls of the one or more insulating layers around the pillar trench exposes a portion of a top surface of the nitride isolation layer.

19. The method of claim 14 , wherein forming the T-plug further comprises:
forming the T-plug in the plug recess and across a top surface of the oxide isolation layer; and
removing a portion of the T-plug to expose the top surface of the oxide isolation layer.

20. The method of claim 1 , further comprising forming an oxide top layer across the T-plug and the oxide isolation layer and wherein forming the electrical contact further comprises forming the electrical contact on the T-plug through the oxide top layer.

Assignees

• Intel Corp

Inventors

• Zhu Hongbin
• Zhao Jun
• Narayanan Purnima
• Haller Gordon
• Fazil Damir

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H01L21/76877

  Electricity · mapped topic

• H01L21/76897

  Electricity · mapped topic