Analog-to-digital converting circuit for optimizing power consumption of dual conversion gain operation, operation method thereof, and image sensor including the same

Patent metadata

Field	Value
Publication number	US-12563318-B2
Application number	US-202318536803-A
Country	US
Kind code	B2
Filing date	Dec 12, 2023
Priority date	Nov 15, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A circuit includes a comparator configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, and a counter configured to count pulses of the first conversion gain output signal, output a counting result as a first digital signal, and determine whether an output of a second digital signal corresponding to the second conversion gain is required, based on the first digital signal. The first conversion gain is higher than the second conversion gain, and based on determining that the output of the second digital signal is not required, the counter is further configured to control the comparator such that the second conversion gain output signal is not generated.

First claim

What is claimed is:

1 . An image sensor comprising:
a pixel array configured to output a first pixel signal corresponding to a first conversion gain from a first pixel and output a second pixel signal corresponding to a second conversion gain from the first pixel; and an analog-to-digital converting circuit configured to output a first digital signal corresponding to the first pixel signal, wherein the analog-to-digital converting circuit is configured to output a second digital signal corresponding to the second pixel signal based on a value of the first digital signal, wherein the first conversion gain is higher than the second conversion gain, and wherein the analog-to-digital converting circuit is configured to output the second digital signal based on a comparison result between a value of at least a portion of bits of the first digital signal and a threshold value.

2 . The image sensor of claim 1 , wherein the pixel array comprises a floating diffusion region connected to the first pixel and a plurality of pixels connected to the floating diffusion region,
wherein the floating diffusion region has a first capacitance value when the pixel array outputs the first pixel signal, and wherein the floating diffusion region has a second capacitance value greater than the first capacitance value when the pixel array outputs the second pixel signal.

3 . The image sensor of claim 2 , wherein the analog-to-digital converting circuit is configured to output the second digital signal when the value of at least a portion of bits of the first digital signal is greater than the threshold value.

4 . The image sensor of claim 3 , wherein the analog-to-digital converting circuit is configured not to generate the second digital signal when the value of at least a portion of bits of the first digital signal is smaller than or equal to the threshold value.

5 . The image sensor of claim 3 , wherein the pixel array further comprises a dual conversion transistor connected to the floating diffusion region and a reset transistor connected to the dual conversion transistor, and
wherein the dual conversion transistor and the reset transistor are connected in series.

6 . The image sensor of claim 3 , wherein the analog-to-digital converting circuit is configured to output a first reset digital signal corresponding to a reset signal of the first pixel signal and the first digital signal before outputting the second digital signal.

7 . The image sensor of claim 5 , wherein the analog-to-digital converting circuit is configured to output a first reset digital signal corresponding to a reset signal of the second pixel signal and a second reset digital signal corresponding to a reset signal of the first pixel signal before outputting the first digital signal.

8 . The image sensor of claim 5 , wherein the at least a portion of bits of the first digital signal includes a most significant bit of the first digital signal.

9 . An image sensor comprising:
a pixel array configured to output a first pixel signal corresponding to a first conversion gain from a first pixel and output a second pixel signal corresponding to a second conversion gain from the first pixel; and an analog-to-digital converting circuit configured to output a first digital signal corresponding to the first pixel signal, wherein the analog-to-digital converting circuit is configured to output a second digital signal corresponding to the second pixel signal based on a value of a most significant bit (MSB) of the first digital signal, wherein the first conversion gain is higher than the second conversion gain, wherein the pixel array comprises a floating diffusion region connected to the first pixel and a plurality of pixels connected to the floating diffusion region, wherein the floating diffusion region has a first capacitance value when the pixel array outputs the first pixel signal, wherein the floating diffusion region has a second capacitance value greater than the first capacitance value when the pixel array outputs the second pixel signal, and wherein the analog-to-digital converting circuit is configured to output the second digital signal based on a comparison result between the value of an MSB of the first digital signal and a threshold value.

10 . The image sensor of claim 9 , wherein the pixel array further comprises a dual conversion transistor connected to the floating diffusion region and a reset transistor connected to the dual conversion transistor, and
wherein the dual conversion transistor and the reset transistor are connected in series.

11 . The image sensor of claim 10 , wherein a number of the plurality of pixels connected to the floating diffusion region is 3.

12 . The image sensor of claim 10 , wherein the analog-to-digital converting circuit comprises:
a comparator configured to convert the first pixel signal into the first digital signal; and a counter configured to compare the value of the MSB of the first digital signal and the threshold value.

13 . The image sensor of claim 12 , further comprising a second floating diffusion region between the dual conversion transistor and the reset transistor.

14 . The image sensor of claim 13 , further comprises a drive transistor configured to receive a power supply voltage, and
wherein the reset transistor is configured to receive the power supply voltage.

15 . The image sensor of claim 14 , wherein the analog-to-digital converting circuit is configured to output the second digital signal when the value of the MSB of the first digital signal is greater than the threshold value.

16 . The image sensor of claim 14 , wherein the analog-to-digital converting circuit is configured not to output the second digital signal when the value of the MSB of the first digital signal is smaller than or equal to the threshold value.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jun Jaehoon
• Lee Youngwoo

Classifications

• H03M1/825

  by comparing the input signal with a digital ramp signal · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title