Dual conversion gain high dynamic range readout for comparator of double ramp analog to digital converter

Patent metadata

Field	Value
Publication number	US-10615190-B2
Application number	US-201916540706-A
Country	US
Kind code	B2
Filing date	Aug 14, 2019
Priority date	Apr 13, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A method includes coupling a low gain input of a dual stage comparator to establish a low conversion gain mode. An analog-to-digital (ADC) operation is performed to determine a low gain reset voltage. A low gain input is decoupled in response to a DCG control signal. A high gain input is coupled to establish a high conversion gain mode in response to the DCG control signal. The ADC operation is performed with the high gain input to determine a high gain reset voltage. The ADC operation is performed with the high gain input to determine a high gain signal voltage. The high gain input is decoupled in response to a DCG control signal transition. The low gain input is recoupled in response to the DCG control signal, and the ADC operation is performed with the low gain input to determine a low gain signal voltage.

First claim

What is claimed is:

1. A method comprising:
coupling a low gain input of a dual stage comparator to inputs and cascode devices to establish a low conversion gain mode in response to a dual conversion gain (DCG) control signal being in a first state;
performing an analog-to-digital (ADC) operation on a pixel with the low gain input to determine a low gain reset voltage of the pixel;
decoupling the low gain input in response to the DCG control signal transitioning to a second state;
coupling a high gain input of the dual stage comparator to the inputs and the cascode devices to establish a high conversion gain mode in response to the DCG control signal transitioning to the second state;
performing an ADC operation on the pixel with the high gain input to determine a high gain reset voltage of the pixel;
performing the ADC operation on the pixel with the high gain input to determine a high gain signal voltage of the pixel, wherein the signal voltage is due to image charge;
decoupling the high gain input in response to the DCG control signal transitioning to the first state;
recoupling the low gain input in response to the DCG control signal transitioning to the first state; and
performing the ADC operation on the pixel with the low gain input to determine a low gain signal voltage of the pixel, wherein the signal voltage is due to image charge.

2. The method of claim 1 , further comprising:
coupling first and second floating diffusions of the pixel to a high reference voltage in response to a reset control signal prior to performing the ADC operation on the pixel with the low gain input to determine a low gain reset voltage of the pixel.

3. The method of claim 1 , further comprising:
coupling first and second floating diffusions to a bitline in response to the e DCG control being in the first state signal prior to performing the ADC operation on the pixel with the low gain input to determine the low gain reset voltage of the pixel.

4. The method of claim 3 , further comprising:
decoupling the second floating diffusion from the bitline in response to the DCG control signal being in the second state prior to performing the ADC operation on the pixel with the high gain input to determine the high gain reset voltage of the pixel.

5. The method of claim 1 , further comprising:
coupling first and second floating diffusions of the pixel to a photodiode of the pixel in response to a transfer control signal.

6. The method of claim 5 , further comprising:
decoupling the first and second floating diffusions of the pixel from the photodiode of the pixel in response to a change in the transfer control signal prior to performing the ADC operation on the pixel with the high gain input to determine the high gain signal voltage of the pixel, wherein the first and second floating diffusions are coupled to a bitline.

7. The method of claim 6 , further comprising:
decoupling the second floating diffusion from the bitline in response to the DCG control signal being in the first state prior to performing the ADC operation on the pixel with the low gain input to determine the low gain signal voltage of the pixel.

Assignees

• Omnivision Tech Inc

Inventors

• Ebihara Hiroaki

Classifications

• H04N5/378

  Electricity · mapped topic

• H01L27/1255 Primary

  Electricity · mapped topic

• H04N25/771 Primary

  comprising storage means other than floating diffusion · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title