Semiconductor chip apparatus and method for checking the integrity of a memory

Patent metadata

Field	Value
Publication number	US-12561483-B2
Application number	US-202318311981-A
Country	US
Kind code	B2
Filing date	May 4, 2023
Priority date	May 12, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A semiconductor chip apparatus including a memory having a plurality of memory locations, a memory access element, and an integrity check device configured to store a reference value for a check function over values stored in the memory locations and, in a case of write access to a memory location, configured to update a check value with the value to be written by the write access if the check value represents the value stored in the memory location prior to the write access, and configured to compare the reference value with the check value after the check value has been generated and output a signal depending on a result of the comparison.

First claim

The invention claimed is:

1 . A semiconductor chip apparatus, comprising:
a memory having a plurality of memory locations; a memory access element configured to read and write data to and from the memory; and an integrity check device configured to:
store a reference value for a check function over values stored in the memory locations;
generate a check value for the check function by reading the memory locations, and starting from an initial value, updating the check value for each read memory location with the value read from the memory location, to include the value,
wherein the integrity check device is configured to perform the reading of the memory locations only during an idle period of processing of the memory access element, during which the memory access element does not access the memory, thereby allowing read and write operations of the memory access element to continue without disruption;
in a case of a write access to a memory location, concurrently update the check value with a value being written by the write access, at the time of the write operation, if the check value represents the check value previously stored in the memory location prior to the write access; and
compare the reference value with the check value, and output a signal depending on a result of the comparison.

2 . The semiconductor chip apparatus as claimed in claim 1 , wherein the integrity check device is further configured to generate the check value during times at which the access element need not provide any data for other receivers.

3 . The semiconductor chip apparatus as claimed in claim 2 , wherein the integrity check device is configured to:
in a case of write access to the memory by the memory access element, verify whether the write access is to a memory location that stores a value that the integrity check device has already used to update the check value for the check function; and if the write access is to a memory location that stores a value that the integrity check device has already updated the check value for the check function, re-read the memory location and adapt the check value to include the value to be written by the memory access rather than the read value.

4 . The semiconductor chip apparatus as claimed in claim 1 , wherein the check function is a commutative operation on a mapping of the stored values.

5 . The semiconductor chip apparatus as claimed in claim 4 , wherein the commutative operation is an XOR combination.

6 . The semiconductor chip apparatus as claimed in claim 1 , wherein the integrity check device is further configured to generate the reference value to represent the values stored in the memory locations, and to adjust the reference value during the write access to represent the value to be written by the write access rather than the value stored in the write-accessed memory location prior to the write access.

7 . The semiconductor chip apparatus as claimed in claim 1 , wherein the memory is a dual port memory with a first port and a second port, the memory access element is configured to access the memory via the first port, and the integrity check device is configured to read the stored values via the second port, wherein the dual port memory enables simultaneous access to the memory by both the memory access element and the integrity check device.

8 . The semiconductor chip apparatus as claimed in claim 1 , wherein, to read one of the stored values to generate the check value, the integrity check device is configured to await a time at which the memory access element does not access the memory.

9 . The semiconductor chip apparatus as claimed in claim 8 , wherein the integrity check device is configured to prohibit access to the memory by the memory access element and to perform a read access to generate the check value on the memory instead if the integrity check device otherwise waits for longer than a maximum period of time for a time at which the memory access element does not access the memory.

10 . The semiconductor chip apparatus as claimed in claim 1 , wherein the memory access element is a data processing unit that accesses the memory, which is a random access memory or one or more registers.

11 . The semiconductor chip apparatus as claimed in claim 1 , wherein the integrity check device is further configured to output the signal when the reference value does not match the check value.

12 . The semiconductor chip apparatus as claimed in claim 1 , wherein the integrity check device is further configured to periodically generate the check value, compare the check value to the reference value, and output the signal depending on a result of the comparison.

13 . A method for checking an integrity of a memory, comprising:
storing a reference value for a check function over values stored in memory locations of the memory; generating a check value for the check function by reading out the memory locations; starting from an initial value, updating the check value for each read memory location with the value read from the memory location such that the check value includes the value for reading out the memory locations, wherein the reading out of the memory locations is performed only during an idle period of processing of a memory access element, during which the memory access element does not access the memory, thereby allowing read and write operations of the memory access element to continue without disruption; in a case of a write access by a memory element to a memory location, concurrently updating the check value with a value being written by the write access, at the time of the write operation, if the check value represents the check value previously stored in the memory location prior to the write access; and comparing the reference value with the check value, and outputting a signal depending on a result of the comparison.

Assignees

• Infineon Technologies Ag

Inventors

• Janke Marcus
• Sonnekalb Steffen

Classifications

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/64 Primary

  Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title