Protection of data on a data path in a memory system

Patent metadata

Field	Value
Publication number	US-11327836-B1
Application number	US-202017037382-A
Country	US
Kind code	B1
Filing date	Sep 29, 2020
Priority date	Sep 29, 2020
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

Some examples herein provide for protection of data on a data path in a memory system in an integrated circuit. In an example, an integrated circuit includes a bit checker circuit, an Error Correcting Code (ECC) encoder circuit, an ECC decoder circuit, and a check bit generation circuit. The bit checker circuit is configured to check write data based on write-path check bit(s). The ECC encoder circuit is configured to generate a write encoded ECC value based on the write data. The write encoded ECC value is to be written to the memory with the write data. The ECC decoder circuit is configured to decode a read encoded ECC value and check read data based on the read encoded ECC value. The read encoded ECC value and read data are read from the memory. The check bit generation circuit is configured to generate read-path check bit(s) from the read data.

First claim

What is claimed is:

1. An integrated circuit comprising:
a bit checker circuit configured to check write data for an error based on one or more write-path check bits, the write data to be written to memory;
an Error Correcting Code (ECC) encoder circuit configured to generate a write encoded ECC value based on the write data, the write encoded ECC value to be written to the memory with the write data;
an ECC decoder circuit configured to decode a read encoded ECC value and check read data for an error based on the read encoded ECC value, the read encoded ECC value and the read data being read from the memory;
a check bit generation circuit configured to generate one or more read-path check bits from the read data; and
a multiplexer stage communicatively coupled to the bit checker circuit and the ECC encoder circuit, and configured to output the write data and the write-path check bits.

2. The integrated circuit of claim 1 , wherein:
the one or more write-path check bits are one or more write-path parity bits;
the bit checker circuit is configured to perform a parity check for a parity error;
the one or more read-path check bits are one or more read-path parity bits; and
the check bit generation circuit is configured to implement a parity bit generation scheme to generate the one or more read-path parity bits.

3. The integrated circuit of claim 1 , wherein the multiplexer stage comprises a first input configured to receive request data of a request and one or more request check bits of the request and having a second input communicatively coupled to the ECC decoder circuit and the check bit generation circuit and configured to receive the read data and the one or more read-path check bits, an output of the multiplexer stage being communicatively coupled to the bit checker circuit and the ECC encoder circuit, the multiplexer stage being configured to selectively output, as the write data, (i) the request data and (ii) a subset of the request data and a subset of the read data, and to selectively output, as the one or more write-path check bits, (i) the one or more request check bits and (ii) a subset of the one or more request check bits and a subset of the one or more read-path check bits.

4. The integrated circuit of claim 3 further comprising a buffer configured to store the request data and the one or more request check bits appended to the request data, the buffer being communicatively coupled to the first input of the multiplexer stage.

5. The integrated circuit of claim 3 further comprising a memory system comprising the ECC encoder circuit, the bit checker circuit, the ECC decoder circuit, the check bit generation circuit, and the multiplexer stage, wherein the memory system is configured to, for a write transaction implemented by the memory system in response to the request:
cause the multiplexer stage to selectively output, as the write data and the one or more write-path check bits, respectively, the request data and the one or more request check bits;
cause the write data and the write encoded ECC value to be written to the memory using an address of the request; and
transmit a write response in response to writing the write data and the write encoded ECC value to the memory.

6. The integrated circuit of claim 3 further comprising a memory system comprising the ECC encoder circuit, the bit checker circuit, the ECC decoder circuit, the check bit generation circuit, and the multiplexer stage, wherein the memory system is configured to, for a read transaction implemented by the memory system in response to the request:
cause the read data to be read from the memory using an address of the request; and
transmit a read response including the read data and the one or more read-path check bits.

7. The integrated circuit of claim 3 further comprising a memory system comprising the ECC encoder circuit, the bit checker circuit, the ECC decoder circuit, the check bit generation circuit, and the multiplexer stage, wherein the memory system is configured to, for a read-modify-write request transaction implemented by the memory system in response to the request:
cause the read data to be read from the memory using an address of the request;
cause the multiplexer stage to selectively output, as the write data, a subset of the request data and a subset of the read data, and to selectively output, as the one or more write-path check bits, a subset of the one or more request check bits and a subset of the one or more read-path check bits;
cause the write data and the write encoded ECC value to be written to the memory using the address of the request; and
transmit a response in response to writing the write data and the write encoded ECC value to the memory.

8. The integrated circuit of claim 1 further comprising a memory system comprising the ECC encoder circuit, the bit checker circuit, the ECC decoder circuit, and the check bit generation circuit, wherein the memory system is configured to, for a write transaction implemented by the memory system in response to a request:
cause the write data and the write encoded ECC value to be written to the memory using an address of the request; and
transmit a write response in response to writing the write data and the write encoded ECC value to the memory.

9. The integrated circuit of claim 1 further comprising a memory system comprising the ECC encoder circuit, the bit checker circuit, the ECC decoder circuit, and the check bit generation circuit, wherein the memory system is configured to, for a read transaction implemented by the memory system in response to a request:
cause the read data to be read from the memory using an address of the request; and
transmit a read response including the read data and the one or more read-path check bits.

10. The integrated circuit of claim 1 further comprising:
a memory system comprising the memory, the ECC encoder circuit, the bit checker circuit, the ECC decoder circuit, and the check bit generation circuit; and
a master circuit configured to access the memory via a communication with the memory system, the master circuit and the memory system being on a same integrated circuit chip.

11. A method comprising:
receiving, by a memory system, a request;
reading read data and a read encoded Error Correcting Code (ECC) value from memory based on the request;
checking, by an ECC decoder circuit of the memory system, the read data based on the read encoded ECC value;
generating, by a check bit generation circuit of the memory system, one or more read-path check bits based on the read data; and
communicating to a bit checker circuit of the memory system and an ECC encoder circuit of the memory system, as write data, a subset of the read data and a subset of request data of the request.

12. The method of claim 11 further comprising transmitting from the memory system a read response that includes the read data and the one or more read-path check bits.

13. The method of claim 11 further comprising:
communicating to the bit checker circuit, as one or more write-path check bits, a subset of the one or more read-path check bits and a subset of one or more request check bits of the request;
checking, by the bit checker circuit, the write data for an error based on the one or more write-path check bits;
generating, by the ECC encoder circuit, a write encoded ECC value based on the write data; and
writing the write data and the write encoded ECC value to the memory of the memory system based on the request.

14. The method of claim 13 further comprising asserting an error signal by the bit checker circuit when the bit checke

Assignees

• Xilinx Inc

Inventors

• Wu Danny Tsung-Heng
• Tran David

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title