Command configuration method, command configuration unit, display processor unit, and electronic device

US12561063B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12561063-B2
Application numberUS-202318566811-A
CountryUS
Kind codeB2
Filing dateSep 19, 2023
Priority dateSep 19, 2023
Publication dateFeb 24, 2026
Grant dateFeb 24, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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The present application provides a command configuration method, a command configuration unit, a display processor unit, and an electronic device and relates to the field of data transmission. The command configuration unit comprises: a readable data channel including a buffer and a selector, the buffer being configured with a plurality of buffer regions; and a plurality of command interfaces, each of the command interfaces being configured to correspond to a different one of the buffer regions, respectively. Each of the command interfaces is configured to be connected to the image processing module. The selector is configured to receive the readable data and store the readable data in a corresponding buffer region according to the identification information. Each of the command interfaces is configured to acquire the readable data from the corresponding buffer region and configure the image processing module based on the configuration command in the readable data.

First claim

Opening claim text (preview).

What is claimed is: 1 . A command configuration unit, comprising: a readable data channel, comprising a buffer and a selector, the buffer being connected to the selector, the buffer being configured with a plurality of buffer regions; the selector being connected to a memory that outputs readable data, the readable data comprising a configuration command and identification information, the configuration command comprising parameters for configuring each image processing module in a display processor unit, and the identification information representing a buffer region corresponding to the readable data; and a plurality of command interfaces, each of which is connected to the buffer, respectively, and each of which is configured to correspond to a different one of the buffer regions, respectively; and each of the command interfaces being connected to a respective image processing module, wherein the selector is configured to receive the readable data and store the readable data in a corresponding buffer region according to the identification information; and each of the command interfaces is configured to acquire the readable data from the corresponding buffer region and configure the respective image processing module based on the configuration command in the readable data, wherein the readable data channel further comprises: an address cache, connected to the buffer and to each of the command interfaces, respectively, wherein the address cache is configured to store a write address of the readable data in the buffer region and a read address of the readable data read out from the buffer region; each of the command interfaces is configured to read the readable data from the buffer region according to the write address; and the selector is configured to store the readable data in the corresponding buffer region according to the read address and the identification information. 2 . The command configuration unit according to claim 1 , further comprising: a read request channel, the read request channel comprising a plurality of read request generators, and each of the read request generators corresponding to a different one of the command interfaces, respectively, wherein each of the read request generators is configured to send a read request to the memory; and the memory is configured to send the readable data to the buffer in response to the read request. 3 . The command configuration unit according to claim 2 , wherein the read request channel further comprises a read request arbiter; and the read request arbiter is connected to each of the read request generators and is configured to be connected to the memory; and the read request arbiter is configured to control an order of output of each of read requests based on a preset output priority rule. 4 . The command configuration unit according to claim 1 , wherein the readable data channel further comprises a base address memory group, the base address memory group comprises a plurality of base address memories, and the address cache is connected to each of the command interfaces through each of the base address memories, respectively; and each of the base address memories is configured to provide the write address for a command interface connected to the one of the base address memories after the readable data is stored in the buffer region. 5 . The command configuration unit according to claim 1 , wherein the readable data channel further comprises a buffered read arbiter; and the buffered read arbiter is connected to the buffer and to each of the command interfaces, respectively; and the buffered read arbiter is configured to instruct each of the command interfaces to acquire the readable data from the buffer. 6 . The command configuration unit according to claim 1 , wherein the buffer regions corresponding to the respective command interfaces share a storage space of the buffer, and a storage space corresponding to each of the buffer regions is allocated according to a quantity of the readable data in the buffer corresponding to each of the command interfaces. 7 . The command configuration unit according to claim 1 , wherein each of the command interfaces comprises a command cache and a command parser, the command cache is connected to the buffer, and the command cache is connected to the command parser; and the command parser is configured to be connected to the image processing module; the command cache is configured to store the readable data acquired from the buffer; and the command parser is configured to output the readable data to the image processing module in a preset format to configure the image processing module. 8 . The command configuration unit according to claim 7 , wherein the command parser comprises a first parser or a second parser; the configuration command comprises a coefficient command, which is configured for configuring an image processing module having a three-dimensional lookup table; and the second parser is configured to output the readable data to the image processing module in accordance with a magnitude of an output bandwidth of the second parser; and the output bandwidth of the second parser in each of the command interfaces matches a bandwidth of each of image processing modules having the three-dimensional lookup table in the display processor unit, respectively. 9 . A display processor unit, comprising: the command configuration unit according to claim 1 ; and a plurality of image processing modules, connected to the command configuration unit, respectively. 10 . An electronic device, comprising: the display processor unit according to claim 9 ; and a controller and a memory, the memory being connected to the controller and the display processor unit, respectively, wherein the controller is configured to generate the readable data and store the readable data into the memory; and the memory is configured to output the readable data to the display processor unit in response to a read request from the display processor unit. 11 . The command configuration unit according to claim 2 , wherein each of the command interfaces comprises a command cache and a command parser, the command cache is connected to the buffer, and the command cache is connected to the command parser; and the command parser is configured to be connected to the image processing module; the command cache is configured to store the readable data acquired from the buffer; and the command parser is configured to output the readable data to the image processing module in a preset format to configure the image processing module. 12 . The command configuration unit according to claim 3 , wherein each of the command interfaces comprises a command cache and a command parser, the command cache is connected to the buffer, and the command cache is connected to the command parser; and the command parser is configured to be connected to the image processing module; the command cache is configured to store the readable data acquired from the buffer; and the command parser is configured to output the readable data to the image processing module in a preset format to configure the image processing module. 13 . The command configuration unit according to claim 1 , wherein each of the command interfaces comprises a command cache and a command parser, the command cache is connected to the buffer, and the command cache is connected to the command parser; and the command parser is configured to be connected to the image processing module; the command cache is configured to store the readable data acquired from the buffer; and the command parser is configured to outpu

Assignees

Inventors

Classifications

  • Single storage device · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • on a point to point bus (G06F13/4247, G06F13/4282 take precedence) · CPC title

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What does patent US12561063B2 cover?
The present application provides a command configuration method, a command configuration unit, a display processor unit, and an electronic device and relates to the field of data transmission. The command configuration unit comprises: a readable data channel including a buffer and a selector, the buffer being configured with a plurality of buffer regions; and a plurality of command interfaces, …
Who is the assignee on this patent?
Verisilicon Microelectronics Chengdu Co Ltd, Verisilicon Microelectronics Shanghai Co Ltd, Verisilicon Microelectronics Nanjing Co Ltd, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06F3/0613. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 24 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).