System and method for batch accessing

Patent metadata

Field	Value
Publication number	US-11093276-B2
Application number	US-201916247519-A
Country	US
Kind code	B2
Filing date	Jan 14, 2019
Priority date	Jan 24, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

Embodiments of the present disclosure provides systems and methods for batch accessing. The system includes a plurality of buffers configured to store data; a plurality of processor cores that each have a corresponding buffer of the plurality of buffers; a buffer controller configured to generate instructions for performing a plurality of buffer transactions on at least some buffers of the plurality of buffers; and a plurality of data managers communicatively coupled to the buffer controller, each data manager is coupled to a corresponding buffer of the plurality of buffers and configured to execute a request for a buffer transaction at the corresponding buffer according to an instruction received from the buffer controller.

First claim

What is claimed is:

1. A system for batch accessing, comprising:
a plurality of buffers configured to store data;
a plurality of processor cores that each have a corresponding buffer of the plurality of buffers;
a buffer controller configured to:
generate instructions for performing a plurality of buffer transactions on at least some buffers of the plurality of buffers,
sequentially perform a first set of buffer transactions on the respective buffers,
determine whether a number of the plurality of buffers is less than a number of the buffer transactions to be performed, and
sequentially perform a second set of buffer transactions on the respective buffers in response to the number of the plurality of buffers being less than the number of the buffer transactions to be performed; and

a plurality of data managers communicatively coupled to the buffer controller, each data manager is coupled to a corresponding buffer of the plurality of buffers and configured to execute a request for a buffer transaction at the corresponding buffer according to an instruction received from the buffer controller.

2. The system according to claim 1 , wherein each buffer includes a plurality of data units, and the instruction received from the buffer controller includes a starting address of the buffer, a number of the buffer transactions to be performed, a number of data units accessed in a buffer transaction.

3. The system according to claim 2 , wherein the starting address includes an identification of a buffer, and the buffer controller is further configured to:
determine a data manager coupled to a buffer for a buffer transaction based on the identification of the buffer; and
distribute the buffer transaction to the determined data manager for execution.

4. The system according to claim 3 , wherein the starting address further includes an offset in the buffer, and the data manager is further configured to execute the buffer transaction by:
determining an initial data unit to start the buffer transaction based on the offset; and
accessing the number of data units of the buffer coupled to the data manager, the number of data units starting from the initial data unit.

5. The system according to claim 2 , wherein the instruction further includes a stride, and the starting address of each buffer transaction in the second set is further offset by the stride.

6. The system according to- claim 1 , wherein each data manager is associated with a predetermined number of buffers.

7. The system according to claim 1 , wherein the buffer transaction includes at least one of a read transaction, a write transaction, or a broadcast transaction.

8. The system according to claim 7 , wherein in response to the buffer transaction including the broadcast transaction, the instruction further includes a data width of data to be broadcasted, and the data width equals a width of accessed data in a data unit.

9. A method for batch accessing a plurality of buffers associated with a processor core array, comprising:
generating, at a buffer controller, an instruction for performing a plurality of buffer transactions on at least some buffers of the plurality of buffers;
acquiring, at a data manager associated with a corresponding buffer of the plurality of buffers, the instruction from the buffer controller;
executing, at the data manager, a request for a buffer transaction at the corresponding buffer according to the instruction;
sequentially performing a first set of buffer transactions on the respective buffers;
determining whether a number of the plurality of buffers is less than a number of the buffer transactions to be performed; and
sequentially performing a second set of buffer transactions on the respective buffers in response to the number of the plurality of buffers being less than the number of the buffer transactions to be performed.

10. The method according to claim 9 , wherein each buffer includes a plurality of data units, and the instruction includes a starting address of the buffer, a number of the buffer transactions to be performed, a number of data units accessed in a buffer transaction.

11. The method according to claim 10 , wherein the starting address includes an identification of a buffer, in generating the instruction for performing the plurality of buffer transactions on at least some buffers of the plurality of buffers, the method further comprises:
determine a data manager coupled to a buffer for a buffer transaction based on the identification of the buffer; and
distribute the buffer transaction to the determined data manager for execution.

12. The method according to claim 11 , wherein the starting address further includes an offset in the buffer, and in executing the buffer transaction at the corresponding buffer according to the instruction, the method further comprises:
determining an initial data unit to start the buffer transaction based on the offset; and
accessing the number of data units of the buffer coupled to the data manager, the number of data units starting from the initial data unit.

13. The method according to claim 10 , wherein the instruction further includes a stride, and the starting address of each buffer transaction in the second set is further offset by the stride.

14. The method according to claim 9 , wherein each data manager is associated with a predetermined number of buffers.

15. The method according to claim 9 , wherein the buffer transaction includes at least one of a read transaction, a write transaction, or a broadcast transaction.

16. The method according to claim 15 , wherein in response to the buffer transaction including broadcast, the instruction further includes a data width of data to be broadcast, and the data width equals a width of accessed data in a data unit.

Assignees

• Alibaba Group Holding Ltd

Inventors

• Zhou Qinggang
• Jin Lingling

Classifications

• G06F15/16 Primary

  Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor G06F9/52; in regulating and control system G05B)} · CPC title

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title