Macro I/O unit for image processor

Patent metadata

Field	Value
Publication number	US-10380969-B2
Application number	US-201615389168-A
Country	US
Kind code	B2
Filing date	Dec 22, 2016
Priority date	Feb 28, 2016
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.

First claim

The invention claimed is:

1. An image processor, comprising:
one or more internal stencil processors each having a respective two-dimensional shift-register array structure;
a sheet generator; and
an I/O unit configured to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory, the I/O unit comprising multiple logical channel units, each logical channel unit comprising:
addressing circuitry configured to generate addresses corresponding to portions of a line group stored in the external memory, and
reformatting circuitry configured to generate reformatted versions of data read from the external memory,

wherein each logical channel unit is configured to form a logical channel between the external memory and a respective line buffer within the image processor,
wherein each logical channel unit is configured to provide reformatted portions of a respective line group stored in the external memory to a line buffer of the image processor including:
using the addressing circuitry to generate addresses corresponding to respective portions of the line group stored in the external memory, including generating an address corresponding to a first full-width area of the line group having a same width as the line group and repeatedly generating addresses corresponding respectively to a plurality of subsequent areas of the line group, each subsequent area of the plurality of subsequent areas having a smaller width than the line group,
using the reformatting circuitry to generate reformatted image data comprising reformatted versions of each portion of the respective line group in multiple different respective color formats, and
providing the reformatted image data to the line buffer,

wherein the sheet generator of the image processor is configured to load, from the line buffer, multiple sheets having different respective reformatted versions of each subsequent area of the line group into different respective spaces of the two-dimensional shift-register array structure of an internal stencil processor of the one or more internal stencil processors.

2. The image processor of claim 1 , wherein each logical channel unit is configured to repeatedly read and provide the plurality of subsequent areas to the line buffer as the sheet generator of the image processor repeatedly consumes each subsequent area from the line buffer.

3. The image processor of claim 2 , wherein the sheet generator is configured to repeatedly consume each subsequent area from the line buffer including generating sheets of image data each having data from both the first full-width area of the line group and a subsequent area of the line group and providing each generated sheet of image data to one of the one or more internal stencil processors of the image processor.

4. The image processor of claim 1 , wherein the reformatting circuitry is configured to repeatedly read from an input queue to generate multiple reformatted versions of each subsequent area of the line group in each of multiple different color formats.

5. The image processor of claim 1 , wherein the each logical channel unit comprises a state machine that is configured to control an ordering of reads between each full-width area of each line group and each subsequent area of each line group.

6. A computing system, comprising:
one or more general purpose processors;
an external memory;
a memory controller coupled to the external memory; and
an image processor, comprising:
one or more internal stencil processors each having a respective two-dimensional shift-register array structure;
a sheet generator; and
an I/O unit configured to read input image data from the external memory for processing by the image processor and to write output image data from the image processor into the external memory, the I/O unit comprising:
multiple logical channel units, each logical channel unit comprising:
addressing circuitry configured to generate addresses corresponding to portions of a line group stored in the external memory, and
reformatting circuitry configured to generate reformatted versions of data read from the external memory,

wherein each logical channel unit is configured to form a logical channel between the external memory and a respective line buffer within the image processor,
wherein each logical channel unit is configured to provide reformatted portions of a respective line group stored in the external memory to a line buffer of the image processor including:
using the addressing circuitry to generate addresses corresponding to respective portions of the line group stored in the external memory, including generating an address corresponding to a first full-width area of the line group having a same width as the line group and repeatedly generating addresses corresponding respectively to a plurality of subsequent areas of the line group, each subsequent area of the plurality of subsequent areas having a smaller width than the line group,
using the reformatting circuitry to generate reformatted image data comprising reformatted versions of each portion of the respective line group in multiple different respective color formats, and
providing the reformatted image data to the line buffer,

wherein the sheet generator of the image processor is configured to load, from the line buffer, multiple sheets having different respective reformatted versions of each subsequent area of the line group into different respective spaces of a two-dimensional shift-register array structure of an internal stencil processor of the one or more internal stencil processors.

7. The computing system of claim 6 , wherein each logical channel unit is configured to repeatedly read and provide the plurality of subsequent areas to the line buffer as the sheet generator of the image processor repeatedly consumes each subsequent area from the line buffer.

8. The computing system of claim 7 , wherein the sheet generator is configured to repeatedly consume each subsequent area from the line buffer including generating sheets of image data each having data from both the first full-width area of the line group and a subsequent area of the line group and providing each generated sheet of image data to one of the one or more internal stencil processors of the image processor.

9. The computing system of claim 6 , wherein the reformatting circuitry is configured to repeatedly read from an input queue to generate multiple reformatted versions of each subsequent area of the line group in each of multiple different color formats.

10. The computing system of claim 6 , wherein at least a portion of the external memory resides within system memory of the computing system.

11. A method performed by an image processor comprising one or more internal stencil processors each having a respective two-dimensional shift-register array structure, the method comprising:
forming, by a logical channel unit of a plurality of logical channel units of an I/O unit of the image processor, a logical channel between an external memory and a line buffer within the image processor;
using, by the logical channel unit, addressing circuitry to generate addresses corresponding to respective portions of a line group stored in the external memory, including generating an address corresponding to a first full-width area of the line group having a same width as the line group and generating addresses corresponding respectively to a plurality of subsequent areas of the line group, each subsequent area of the plurality of subsequent areas having a smaller width than the line group;
using reformatting circuitry of the logical c

Assignees

• Google Llc

Inventors

• Meixner Albert
• Desai Neeti
• Manatunga Dilan
• Redgrave Jason Rupert
• Mark William

Classifications

• G09G5/006 Primary

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G09G2340/02

  Handling of images in compressed format, e.g. JPEG, MPEG · CPC title

• G09G5/02

  characterised by the way in which colour is displayed {(details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607)} · CPC title