Semiconductor structure including multiple barrier layers and method for forming the same

Patent metadata

Field	Value
Publication number	US-12557619-B2
Application number	US-202217837783-A
Country	US
Kind code	B2
Filing date	Jun 10, 2022
Priority date	Jun 10, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a transistor on the substrate; a first dielectric layer over the transistor; a second dielectric layer over the first dielectric layer; a barrier layer extending from the second dielectric layer to the first dielectric layer; and a conductive structure separated from the second dielectric layer and the first dielectric layer by the barrier layer. The barrier layer includes: a first layer, including titanium or tantalum along inner sidewalls of the first dielectric layer and the second dielectric layer; a second layer, being an oxide of titanium or tantalum and over the first layer; and a third layer, including cobalt and over the second layer.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor structure, comprising:
providing a substrate; forming a transistor on the substrate; forming a first dielectric layer over the transistor; forming a second dielectric layer over the first dielectric layer; etching the first dielectric layer to form a first contact hole; etching the second dielectric layer to form a second contact hole connected with the first contact hole; forming a barrier layer within the first contact hole and the second contact hole; and depositing a conductive material on the barrier layer to fill the first contact hole and the second contact hole, wherein the forming of the barrier layer comprises:
forming a first layer including titanium or tantalum along inner sidewalls of the first dielectric layer and the second dielectric layer under a first pressure; and
introducing a source gas including cobalt to the first layer under a second pressure greater than the first pressure to form a second layer comprising an oxide of the first layer and a third layer comprising a cobalt-containing layer including a portion of the oxide.

2 . The method of claim 1 , wherein the first pressure is between about 10 −8 torr and about 10 −7 torr.

3 . The method of claim 1 , wherein the second pressure is greater than about 10 −7 torr.

4 . The method of claim 1 , wherein the second layer and the third layer are in-situ formed.

5 . The method of claim 1 , wherein the first layer is formed in a first chamber and the third layer is formed in a second chamber different from the first chamber, and the substrate is transferred from the first chamber to the second chamber without breaking vacuum.

6 . The method of claim 5 , wherein the first layer is oxidized in the second chamber.

7 . The method of claim 1 , wherein the second layer binds the third layer after the third layer is formed.

8 . A method of manufacturing a semiconductor structure, comprising:
forming a transistor on a substrate; forming a first dielectric layer over the transistor; forming a second dielectric layer over the first dielectric layer; recessing the first dielectric layer and the second dielectric layer to form a contact hole; conformally forming a tantalum-containing layer within the contact hole under a first pressure; introducing a source gas including cobalt to the tantalum-containing layer to form an oxide of the tantalum-containing layer and a cobalt-containing layer including a portion of the oxide; and filling the contact hole by depositing a conductive material on the cobalt-containing layer.

9 . The method of claim 8 , wherein the oxide is simultaneously formed when forming the cobalt-containing layer.

10 . The method of claim 8 , wherein the oxide is formed in-situ during the formation of the cobalt-containing layer.

11 . The method of claim 8 , wherein the oxide has a strong affinity to the cobalt-containing layer.

12 . The method of claim 8 , wherein the oxide is crystalline.

13 . The method of claim 12 , wherein the oxide of the tantalum-containing layer has an atomic ratio of oxygen to tantalum less than about 1.

14 . The method of claim 12 , wherein the oxide of the tantalum-containing layer has an atomic ratio of oxygen to tantalum more than about 0.02.

15 . A method of manufacturing a semiconductor structure, comprising:
forming a dielectric layer over a transistor; recessing the dielectric layer to form a contact hole; conformally forming a barrier layer within the contact hole; and depositing a conductive material on the barrier layer to fill the contact hole, wherein the forming of the barrier layer includes:
forming a first layer including titanium along inner sidewalls of the dielectric layer under a first pressure; and
introducing a source gas including cobalt to the first layer to form a second layer comprising an oxide of the first layer and a third layer comprising a cobalt-containing layer including a portion of the oxide.

16 . The method of claim 15 , wherein a thickness ratio between the first layer and the second layer is about 5:1.

17 . The method of claim 15 , wherein a thickness ratio between the second layer and the third layer is about 1:2.

18 . The method of claim 15 , wherein the second layer is crystalline.

19 . The method of claim 15 , wherein the second layer is formed in-situ during the formation of the third layer.

20 . The method of claim 15 , wherein the first layer, the second layer and the third layer are formed in a same chamber.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nian Jun-Nan
• Liang Yao-Hsiang
• Tung Ju Po
• Liu Chieh-Min
• Chung Ming-Ching

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title