Contact structures in light-emitting diode chips for reduced voiding of bonding metals

Patent metadata

Field	Value
Publication number	US-12557443-B2
Application number	US-202318302168-A
Country	US
Kind code	B2
Filing date	Apr 18, 2023
Priority date	Jun 1, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly contact structures in LED chips for reducing voiding of bonding metals are disclosed. LED chips include active LED structures on carrier submounts and contact structures arranged to receive external electrical connections adjacent the active LED structures. Exemplary contact structures include contacts electrically coupled to active LED structures and dielectric structures beneath the contacts. Dielectric structures are arranged beneath portions of the contacts while still allowing electrical connections therethrough. Such dielectric structures may be provided as regions of dielectric material with spacings that control topography of underlying bonding metals to reduce voiding.

First claim

What is claimed is:

1 . A light-emitting diode (LED) chip, comprising:
a carrier submount; an active LED structure bonded to the carrier submount, the active LED structure comprising an n-type layer, a p-type layer, and an active layer that is between the n-type layer and the p-type layer, the active LED structure forming a mesa with mesa sidewalls that define a perimeter of the active LED structure; a contact on the carrier submount in a position that is outside the mesa sidewalls; a barrier layer forming an electrically conductive path between the active LED structure and the contact; and a dielectric structure between the contact and the barrier layer, the dielectric structure comprising at least one dielectric region positioned entirely beneath an area of the contact, the barrier layer electrically connecting with the contact adjacent the at least one dielectric region beneath the contact.

2 . The LED chip of claim 1 , wherein at least one the dielectric region defines a width where the barrier layer electrically connects with the contact, and the width is less than or equal to 11 microns (μm).

3 . The LED chip of claim 1 , wherein the at least one dielectric region is one of a plurality of regions of dielectric material that are registered below the contact.

4 . The LED chip of claim 3 , wherein the plurality of regions of dielectric material are arranged with a pitch that is less than or equal to 11 microns (μm).

5 . The LED chip of claim 3 , wherein the plurality of regions of dielectric material form a plurality of stripes below the contact.

6 . The LED chip of claim 3 , wherein the plurality of regions of dielectric material form a plurality of islands below the contact.

7 . The LED chip of claim 1 , further comprising:
a dielectric reflective layer on the active LED structure; and a metal reflective layer on the dielectric reflective layer and electrically coupled to the active LED structure through the dielectric reflective layer, wherein the dielectric structure comprises a same material as the dielectric reflective layer.

8 . The LED chip of claim 1 , further comprising:
a dielectric reflective layer on the active LED structure; and a metal reflective layer on the dielectric reflective layer and electrically coupled to the active LED structure through the dielectric reflective layer, wherein the dielectric structure comprises a different material than the dielectric reflective layer.

9 . The LED chip of claim 1 , further comprising an n-contact metal electrically coupled with the n-type layer, wherein a portion of the n-contact metal extends to a position that is beneath the contact and between the barrier layer and the carrier submount.

10 . The LED chip of claim 9 , further comprising a passivation layer that is between the barrier layer and the n-contact metal.

11 . The LED chip of claim 10 , wherein the n-contact metal forms a contour shape beneath the contact, and the contour shape is defined by a shape of the dielectric structure.

12 . A light-emitting diode (LED) chip, comprising:
a carrier submount; an active LED structure bonded to the carrier submount, the active LED structure comprising an n-type layer, a p-type layer, and an active layer that is between the n-type layer and the p-type layer, the active LED structure forming a mesa with mesa sidewalls that define a perimeter of the active LED structure; a p-contact on the carrier submount in a position that is outside the mesa sidewalls; a barrier layer forming an electrically conductive path between the p-type layer and the p-contact; and a dielectric structure beneath the p-contact in a position that is between the barrier layer and the p-contact, the dielectric structure comprising at least one dielectric region positioned entirely beneath an area of the p-contact, the barrier layer conformally covering the at least one dielectric region and electrically connecting with the p-contact adjacent the dielectric structure beneath the p-contact.

13 . The LED chip of claim 12 , wherein the at least one dielectric region is one of a plurality of dielectric regions that are beneath the p-contact, and the barrier layer electrically connects with the p-contact between adjacent dielectric regions of the plurality of dielectric regions.

14 . The LED chip of claim 13 , wherein the plurality of dielectric regions is arranged with a pitch in a range from 0.5 microns (μm) to less than or equal to 11 μm.

15 . The LED chip of claim 13 , wherein the plurality of dielectric regions form a plurality of stripes beneath the p-contact.

16 . The LED chip of claim 13 , wherein the plurality of dielectric regions form a plurality of islands beneath the p-contact.

17 . The LED chip of claim 12 , further comprising:
a dielectric reflective layer on the active LED structure; and a metal reflective layer on the dielectric reflective layer and electrically coupled to the p-type layer through the dielectric reflective layer, wherein the dielectric structure comprises a same material as the dielectric reflective layer.

18 . The LED chip of claim 12 , further comprising:
a dielectric reflective layer on the active LED structure; and a metal reflective layer on the dielectric reflective layer and electrically coupled to the p-type layer through the dielectric reflective layer, wherein the dielectric structure comprises a different material than the dielectric reflective layer.

19 . The LED chip of claim 12 , further comprising an n-contact metal electrically coupled with the n-type layer, wherein a portion of the n-contact metal extends to a position that is beneath the p-contact and between the barrier layer and the carrier submount, and wherein the n-contact metal forms a contour shape beneath the p-contact and the contour shape is defined by a shape of the dielectric structure.

20 . The LED chip of claim 19 , further comprising a passivation layer that is between the barrier layer and the n-contact metal.

Assignees

• Creeled Inc

Inventors

• Check Michael
• White Justin
• Wuester Steven
• Hall Nikolas
• Haberern Kevin
• Blakely Colin
• Reiherzer Jesse

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/8506

  Containers · CPC title

• H10H20/857 Primary

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/841

  Reflective coatings, e.g. dielectric Bragg reflectors · CPC title

• H10H20/835

  Reflective materials · CPC title