Interconnects for light emitting diode chips

Patent metadata

Field	Value
Publication number	US-10879441-B2
Application number	US-201816222173-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Dec 17, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.

First claim

What is claimed is:

1. A light emitting diode (LED) chip, comprising:
an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer;
a plurality of first interconnects electrically connected to the n-type layer; and
a plurality of second interconnects electrically connected to the p-type layer, wherein the plurality of first interconnects and the plurality of second interconnects collectively form a symmetric pattern across an area of the LED chip, and wherein diameters of the plurality of second interconnects are different based on a relative position of each individual second interconnect to an individual first interconnect of the plurality of first interconnects.

2. The LED chip of claim 1 , further comprising an n-contact electrically connected to the n-type layer, wherein the plurality of first interconnects comprise a plurality of n-contact interconnects that are electrically connected between the n-contact and the n-type layer.

3. The LED chip of claim 1 , further comprising a reflective structure on the p-type layer, wherein the reflective structure comprises a dielectric layer and a metal layer, and the plurality of second interconnects comprise a plurality of reflective layer interconnects that extend through a portion of the dielectric layer.

4. The LED chip of claim 1 , wherein the plurality of first interconnects are arranged to be evenly spaced from one another in a first pattern across the area of the LED chip and the plurality of second interconnects are arranged to be evenly spaced from one another in a second pattern across the area of the LED chip.

5. The LED chip of claim 4 , wherein the first pattern and the second pattern collectively form the symmetric pattern across the LED chip.

6. The LED chip of claim 1 , wherein a diameter of an individual second interconnect that is arranged closest to a particular first interconnect is larger than a diameter of another individual second interconnect that is arranged farther from the particular first interconnect.

7. The LED chip of claim 1 , wherein a diameter of an individual second interconnect that is arranged closest to a particular first interconnect is smaller than a diameter of another individual second interconnect that is arranged farther from the particular first interconnect.

8. The LED chip of claim 1 , wherein diameters of the plurality of first interconnects are different based on a relative position of each individual first interconnect across the area of the LED chip.

9. The LED chip of claim 1 , wherein diameters of the plurality of first interconnects progressively decrease in a direction from a perimeter of the LED chip toward a center of the LED chip.

10. The LED chip of claim 1 , wherein the plurality of first interconnects and the plurality of second interconnects collectively form an asymmetric pattern in a different area of the LED chip.

11. A light emitting diode (LED) chip, comprising:
an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer;
a plurality of first interconnects electrically connected to the n-type layer; and
a plurality of second interconnects electrically connected to the p-type layer, the plurality of second interconnects comprising diameters that vary within in a range of 2 microns to 15 microns;
wherein a center point of each of the plurality of first interconnects and a center point of each of the plurality of second interconnects form an array of equally spaced center points across the LED chip.

12. The LED chip of claim 11 , further comprising an n-contact electrically connected to the n-type layer, wherein the plurality of first interconnects comprise a plurality of n-contact interconnects that are electrically connected between the n-contact and the n-type layer.

13. The LED chip of claim 11 , further comprising a reflective structure on the p-type layer, wherein the reflective structure comprises a dielectric layer and a metal layer, and the plurality of second interconnects comprise a plurality of reflective layer interconnects that extend through a portion of the dielectric layer.

14. The LED chip of claim 11 , wherein each of the plurality of first interconnects comprises a same diameter that is in a range of 4 microns to 25 microns.

15. The LED chip of claim 11 , wherein the plurality of first interconnects comprise diameters that vary within in a range of 4 microns to 25 microns.

16. The LED chip of claim 11 , wherein each of the plurality of second interconnects comprises a same diameter that is in a range of 2 microns to 15 microns.

17. A light emitting diode (LED) chip, comprising:
an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer;
a first interconnect electrically connected to the n-type layer; and
a plurality of second interconnects electrically connected to the p-type layer;
wherein diameters of at least some second interconnects of the plurality of second interconnects progressively decrease and increase with increasing distance away from the first interconnect.

18. The LED chip of claim 17 , further comprising a plurality of first interconnects that are arranged to be evenly spaced from one another in a first pattern across an area of the LED chip and the plurality of second interconnects are arranged to be unevenly spaced from one another across the area of the LED chip.

19. The LED chip of claim 17 , further comprising a plurality of first interconnects, wherein diameters of the plurality of first interconnects are different based on a relative position of each individual first interconnect across an area of the LED chip.

20. A light emitting diode (LED) chip, comprising:
an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer;
a first interconnect electrically connected to the n-type layer;
a plurality of second interconnects electrically connected to the p-type layer; and
a reflective structure on the p-type layer, wherein the reflective structure comprises a dielectric layer and a metal layer, and the plurality of second interconnects comprise a plurality of reflective layer interconnects that extend through a portion of the dielectric layer;
wherein spacings between adjacent second interconnects of the plurality of second interconnects are different based on a relative position of each second interconnect to the first interconnect.

21. The LED chip of claim 20 , wherein the first interconnect is one of a plurality of first interconnects.

22. The LED chip of claim 21 , wherein the plurality of first interconnects and the plurality of second interconnects collectively form a symmetric pattern across an area of the LED chip.

23. The LED chip of claim 21 , wherein the plurality of first interconnects and the plurality of second interconnects collectively form an asymmetric pattern across an area of the LED chip.

Assignees

• Cree Inc

Inventors

• Check Michael

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10H20/825

  containing nitrogen, e.g. GaN · CPC title

• H10H20/857 Primary

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/84

  Coatings, e.g. passivation layers or antireflective coatings · CPC title