Light-emitting diode chip structures

Patent metadata

Field	Value
Publication number	US-11094848-B2
Application number	US-201916542458-A
Country	US
Kind code	B2
Filing date	Aug 16, 2019
Priority date	Aug 16, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.

First claim

What is claimed is:

1. A light-emitting diode (LED) chip, comprising:
an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer, the active LED structure forming a first opening that extends through the p-type layer, the active layer, and a first portion of the n-type layer;
a passivation layer in the first opening and on a first surface of the n-type layer that is within the first opening, the n-type layer forming a second opening that extends from the first surface of the n-type layer and through a second portion of the n-type layer; and
an n-contact interconnect that extends through the first surface of the n-type layer to electrically connect with a second surface of the n-type layer;
wherein the p-type layer, the active layer, and the n-type layer form an active LED structure mesa, and a third surface of the n-type layer forms a peripheral mesa border of the active LED structure mesa.

2. The LED chip of claim 1 , wherein the first surface of the n-type layer and the second surface of the n-type layer are arranged along different horizontal planes of the n-type layer.

3. The LED chip of claim 1 , wherein the second opening is devoid of the passivation layer.

4. The LED chip of claim 1 , wherein a lateral diameter of the first opening is greater than a lateral diameter of the second opening.

5. The LED chip of claim 1 , wherein the third surface of the n-type layer is arranged along a same horizontal plane as the first surface of the n-type layer.

6. The LED chip of claim 1 , wherein the active LED structure is bonded to a carrier submount such that the p-type layer is closer to the carrier submount than the n-type layer.

7. The LED chip of claim 6 , wherein at least one bonding metal layer is arranged between the p-type layer and the carrier submount.

8. The LED chip of claim 1 , further comprising a light-transmissive substrate.

9. The LED chip of claim 1 , further comprising a reflective structure on the p-type layer, wherein the reflective structure comprises a dielectric reflective layer and a metal reflective layer.

10. The LED chip of claim 9 , wherein the metal reflective layer forms a plurality of reflective layer interconnects that extend through an entire thickness of the dielectric reflective layer.

11. The LED chip of claim 1 , further comprising:
a carrier submount bonded to the active LED structure such that a peripheral border of the carrier submount is devoid of the active LED structure, wherein the passivation layer forms a first passivation layer that is arranged between the active LED structure and the carrier submount, and the first passivation layer is further arranged to extend along the peripheral border; and
a second passivation layer arranged along the peripheral border such that the second passivation layer is laterally spaced from the active LED structure by the first passivation layer.

12. The LED chip of claim 1 , further comprising:
a carrier submount bonded to the active LED structure such that a peripheral border of the carrier submount is devoid of the active LED structure;
a dielectric reflective layer and a barrier layer on the p-type layer, wherein the dielectric reflective layer and the barrier layer are further arranged to extend along the peripheral border; and
a p-contact arranged along the peripheral border, the p-contact further arranged to extend through the dielectric reflective layer to electrically connect with the barrier layer at the peripheral border.

13. A light-emitting diode (LED) chip, comprising:
an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer, the active LED structure forming an active LED structure mesa with a peripheral mesa border that is arranged along a first horizontal plane of the n-type layer; and
an n-contact interconnect that is arranged through the p-type layer, the active layer, and a portion of the n-type layer such that the n-contact interconnect is electrically connected to the n-type layer along a second horizontal plane of the n-type layer that is different than the first horizontal plane of the n-type layer, wherein the first horizontal plane is arranged closer to the active layer than the second horizontal plane.

14. The LED chip of claim 13 , wherein the active LED structure is bonded to a carrier submount.

15. The LED chip of claim 13 , further comprising a light-transmissive substrate.

16. A light-emitting diode (LED) chip, comprising:
an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer;
a carrier submount bonded to the active LED structure such that a peripheral border of the carrier submount is devoid of the active LED structure;
a first passivation layer arranged between the active LED structure and the carrier submount, the first passivation layer further arranged to extend along the peripheral border; and
a second passivation layer arranged along only on the peripheral border such that the second passivation layer is laterally spaced from the active LED structure by the first passivation layer.

17. The LED chip of claim 16 , wherein the second passivation layer comprises silicon dioxide.

18. The LED chip of claim 16 , wherein the first passivation layer comprises silicon nitride.

19. The LED chip of claim 16 , wherein the second passivation layer comprises a plurality of alternating layers of dielectric materials.

20. The LED chip of claim 16 , wherein the second passivation layer forms a stripe along the peripheral border.

21. The LED chip of claim 16 , further comprising a third passivation layer that is over the active LED structure such that a portion of the active LED structure is between the third passivation layer and the carrier submount, the third passivation layer is further arranged over the first passivation layer and the second passivation layer on the peripheral border of the carrier submount.

22. The LED chip of claim 21 , wherein an interface is formed between the first passivation layer and the third passivation layer along the peripheral border of the carrier submount and the interface is closer to the active LED structure than the second passivation layer.

23. The LED chip of claim 16 , further comprising a bonding material arranged between the carrier submount and the active LED structure and along the peripheral border of the carrier submount.

24. The LED chip of claim 23 , wherein along the peripheral border, the bonding material forms a first thickness adjacent a lateral edge of the carrier submount that is less than a second thickness of the bonding material along the peripheral border.

25. The LED chip of claim 16 , further comprising a reflective structure on the p-type layer, wherein the reflective structure comprises a dielectric reflective layer and a metal reflective layer.

26. The LED chip of claim 25 , wherein the dielectric reflective layer and the second passivation layer comprise the same material.

27. The LED chip of claim 16 , further comprising an n-contact interconnect that is electrically connected to the n-type layer, wherein:
the active LED structure forms a first opening that extends through the p-type layer, the active layer, and a first portion of the n-type layer;
the

Assignees

• Cree Inc
• Creeled Inc

Inventors

• Breva Luis
• Stuart Colin
• Check Michael

Classifications

• H10H20/825

  containing nitrogen, e.g. GaN · CPC title

• H10H20/82

  Roughened surfaces, e.g. at the interface between epitaxial layers · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/841

  Reflective coatings, e.g. dielectric Bragg reflectors · CPC title

• H10H20/835

  Reflective materials · CPC title