Memory system packaging structure, and method for forming the same

Patent metadata

Field	Value
Publication number	US-12557300-B2
Application number	US-202318097481-A
Country	US
Kind code	B2
Filing date	Jan 16, 2023
Priority date	Dec 28, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.

First claim

What is claimed is:

1 . A memory system packaging structure, comprising:
memory modules comprising a first memory module and a second memory module, each memory module comprising memory dies stacked in a vertical direction; a memory controller, wherein the first memory module and the second memory module are respectively positioned on two sides of the memory controller; a redistribution layer electrically having a first surface connected to the memory controller; a plastic encapsulation layer encapsulating the memory modules, the memory controller, and the redistribution layer; and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules,
wherein each connecting pillar comprises:
a first portion being in physical contact with one of the memory dies; and
a second portion being in physical contact with the redistribution layer.

2 . The memory system packaging structure according to claim 1 , wherein the first memory module has a first distance from the memory controller, the second memory module has a second distance from the memory controller, and the first distance is the same as the second distance.

3 . The memory system packaging structure according to claim 2 , wherein the first memory module, the second memory module, and the memory controller are arranged in a straight line, such that the memory controller is located between the first memory module and the second memory module.

4 . The memory system packaging structure according to claim 3 , wherein edges of two adjacent dies of the stacked dies are misaligned such that an upper one of the two adjacent dies has an extended portion located beyond a lower one of the two adjacent dies, and the lower one of the two adjacent dies has an uncovered portion located beyond the upper one of the two adjacent dies; and
the uncovered portion of the lower one of the two adjacent dies includes a bonding pad.

5 . The memory system packaging structure according to claim 4 , wherein the first memory module comprises first memory dies misaligned in a first direction by a third distance, and the second memory module comprises second memory dies misaligned in a second direction by a fourth distance, and the third distance is equal to the fourth distance.

6 . The memory system packaging structure according to claim 5 , wherein the first memory dies and the second memory dies are both stacked in the vertical direction, the first direction and the second direction are both perpendicular to the vertical direction, and the first direction is opposite to the second direction.

7 . The memory system packaging structure according to claim 6 , wherein a first number of the first memory dies is equal to a second number of the second memory dies.

8 . The memory system packaging structure according to claim 7 , wherein one connecting pillar in the first memory module is physically attached to the bonding pad of one of a first subset of the first memory dies, while a second subset of memory dies of the first memory dies are connected to the first portion of the connecting pillar in the first memory module by bonding wires; and
one connecting pillar in the second memory module is physically attached to the bonding pad of one of a second subset of the second memory dies, while a second subset of memory dies of the second memory dies are connected to the first portion of the connecting pillar in the second memory module by bonding wires.

9 . The memory system packaging structure according to claim 7 , wherein each connecting pillar in the first memory module is respectively physically attached to the bonding pad of each of the first memory dies; and
each connecting pillar in the second memory module is respectively physically attached to the bonding pad of each of the second memory dies.

10 . The memory system packaging structure according to claim 8 , wherein the one or more connecting pillars comprise one or more copper pillars.

11 . The memory system packaging structure according to claim 10 , further comprising:
metal solder balls located on a second surface of the redistribution layer, wherein the metal solder balls are electrically connected to the memory modules and the memory controller through the redistribution layer, and the second surface and the first surface are opposite to each other.

12 . The memory system packaging structure according to claim 11 , further comprising:
at least one passive device encapsulated in the plastic encapsulation layer, wherein the at least one passive device is disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer.

13 . The memory system packaging structure according to claim 12 , wherein the first memory dies and the second memory dies comprise three-dimensional NAND flash memory dies.

14 . A memory system packaging structure, comprising:
a memory module, comprising memory dies stacked in a vertical direction; a memory controller; a redistribution layer having a first surface electrically connected to the memory controller; a plastic encapsulation layer encapsulating the memory module, the memory controller, and the redistribution layer; and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory module, wherein each connecting pillar comprises:
a first portion being in physical contact with one of the memory dies; and
a second portion being in physical contact with the redistribution layer,
wherein edges of two adjacent dies of the stacked dies are misaligned such that an upper one of the two adjacent dies has an extended portion located beyond a lower one of the two adjacent dies, and the lower one of the two adjacent dies has an uncovered portion located beyond the upper one of the two adjacent dies; and the uncovered portion of the lower one of the two adjacent dies includes a bonding pad.

15 . The memory system packaging structure according to claim 14 , wherein one connecting pillar in the memory module is physically attached to the bonding pad of one of a first subset of the memory dies, while a second subset of memory dies of the memory dies are connected to the first portion of the one connecting pillar in the memory module by bonding wires.

16 . The memory system packaging structure according to claim 14 , wherein at least two connecting pillars in the memory module are respectively physically attached to two bonding pads of two of a first subset of the memory dies, while a second subset of memory dies of the memory dies are connected to first portions of the two connecting pillars in the memory module by bonding wires.

17 . The memory system packaging structure according to claim 14 , wherein each connecting pillar in the memory module is respectively physically attached to the bonding pad of each of the memory dies.

18 . A method for packaging a memory system, comprising:
providing memory modules including a first memory module and a second memory module, each memory module comprising memory dies stacked in a vertical direction, and one or more connecting pillars configured for providing electric power to the memory modules; providing a memory controller having a lead-out pad; mounting the memory modules and the memory controller to a first surface of a redistribution layer, wherein the first memory module and the second memory module are respectively positioned on two sides of the memory controller, and the redistribution

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zeng Xinru
• Chen Peng
• Zhou Houde

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title