Embedded ReRAM with backside contact

Patent metadata

Field	Value
Publication number	US-12557295-B2
Application number	US-202218065117-A
Country	US
Kind code	B2
Filing date	Dec 13, 2022
Priority date	Dec 13, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A semiconductor structure including a one-transistor one-capacitor (1T1R) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.

First claim

What is claimed is:

1 . A semiconductor structure comprising:
a transistor located in a memory device region and comprising a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure; a resistive random access memory (ReRAM) located in the memory device region and positioned above the transistor; a frontside contact structure electrically connecting the ReRAM to the source region of the transistor; and a backside contact structure electrically connecting the drain region of the transistor to a backside back-end-of-the-line (BEOL) structure.

2 . The semiconductor structure of claim 1 , wherein the transistor is a nanosheet transistor comprising a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets, and wherein the gate structure of the transistor wraps around a middle portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced apart semiconductor channel material nanosheets.

3 . The semiconductor structure of claim 2 , further comprising a bottom dielectric isolation layer and a backside interlayer dielectric material layer located beneath the nanosheet transistor, wherein the backside contact structure passes through both the backside interlayer dielectric material layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor.

4 . The semiconductor structure of claim 1 , further comprising a source/drain contact structure positioned between the frontside contact structure and the source region of the transistor, wherein the frontside contact structure is in direct physical contact with a first surface of the source/drain contact structure, and a second surface of the source/drain contact structure opposite the first surface, is in direct physical contact with the source region of the transistor.

5 . The semiconductor structure of claim 1 , further comprising a frontside BEOL structure located above the ReRAM, wherein the frontside BEOL structure is electrically connected to a top electrode of the ReRAM by a frontside BEOL-to-ReRAM metal via.

6 . The semiconductor structure of claim 5 , wherein the frontside BEOL-to-ReRAM metal via passes through a dielectric material layer that is present on the ReRAM.

7 . The semiconductor structure of claim 5 , further comprising a carrier wafer located on a surface of the frontside BEOL structure.

8 . The semiconductor structure of claim 1 , wherein the ReRAM is embedded in a frontside interlayer dielectric material layer.

9 . The semiconductor structure of claim 1 , further comprising a logic device area located adjacent to the memory device region, wherein the logic device area comprises another transistor, the another transistor comprising another gate structure, another source region located on a first side of the another gate structure, and another drain region located on a second side of the another gate structure, wherein the second side of the another gate structure is opposite the first side of the another gate structure.

10 . The semiconductor structure of claim 9 , further comprising another frontside contact structure electrically connecting the another source region of the another transistor to a frontside BEOL structure, and another backside contact structure electrically connecting the another drain region of the another transistor to a backside BEOL structure.

11 . A semiconductor structure comprising:
a transistor located in a memory device region and comprising a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure; a resistive random access memory (ReRAM) located in the memory device region and positioned beneath the transistor; a frontside contact structure electrically connecting the source region of the transistor to a frontside back-end-of-the-line (BEOL) structure; a backside contact structure electrically connecting the drain region of the transistor to the ReRAM; and a backside BEOL structure located beneath the ReRAM, wherein the backside BEOL structure is electrically connected to a bottom electrode of the ReRAM by a backside BEOL-to-ReRAM metal via.

12 . The semiconductor structure of claim 11 , wherein the transistor is a nanosheet transistor comprising a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets, and wherein the gate structure of the transistor wraps around a middle portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced apart semiconductor channel material nanosheets.

13 . The semiconductor structure of claim 12 , further comprising a bottom dielectric isolation layer and a backside interlayer dielectric material layer located beneath the nanosheet transistor, wherein the backside contact structure passes through both the backside interlayer dielectric material layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor.

14 . The semiconductor structure of claim 11 , further comprising a source/drain contact structure positioned between the frontside contact structure and the source region of the transistor, wherein the frontside contact structure is in direct physical contact with a first surface of the source/drain contact structure, and a second surface of the source/drain contact structure opposite the first surface, is in direct physical contact with the source region of the transistor.

15 . The semiconductor structure of claim 11 , further comprising a frontside metal via positioned between the frontside contact structure and the frontside BEOL structure, wherein the frontside metal via has a first surface directly contacting the frontside BEOL structure, and a second surface, that is opposite the first surface, directly contacting frontside contact structure.

16 . The semiconductor structure of claim 11 , further comprising a carrier wafer located on a surface of the frontside BEOL structure.

17 . The semiconductor structure of claim 11 , wherein the ReRAM is embedded in a backside interlayer dielectric material layer.

18 . The semiconductor structure of claim 11 , further comprising a logic device area located adjacent to the memory device region, wherein the logic device area comprises another transistor, the another transistor comprising another gate structure, another source region located on a first side of the another gate structure, and another drain region located on a second side of the another gate structure, wherein the second side of the another gate structure is opposite the first side of the another gate structure.

19 . The semiconductor structure of claim 18 , further comprising another frontside contact structure electrically connecting the another source region of the another transistor to a frontside BEOL structure, and another backside contact structure electrically connecting the another drain region of the another transistor to a backside BEOL structure.

Assignees

• IBM

Inventors

• Sung Min Gyu
• Frougier Julien
• Xie Ruilong
• Park Chanro
• Li Juntao
• Seo Soon-Cheon
• Ando Takashi
• Zhang Chen
• Wu Heng

Classifications

• H10B63/30 Primary

  comprising selection components having three or more electrodes, e.g. transistors · CPC title