Methods used in forming a memory array comprising strings of memory cells including selectively etching sacrificial material in a memory-cell region selectively relative to insulating, insulator and/or insulative material(s) to form void spaces between conductive tiers

Patent metadata

Field	Value
Publication number	US-12557274-B2
Application number	US-202217710262-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Mar 31, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A memory array comprising strings of memory cells comprises a vertical stack comprising vertically-alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material-string constructions of memory-cell strings extend through the insulative and conductive tiers. The channel material of the channel-material-string constructions directly electrically couples with conductor material of the conductor tier. The vertical stack comprising a memory-cell region comprises memory cells. Individual of the insulative tiers in the memory-cell region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being void space. The vertical stack comprises an upper region directly above the memory-cell region. The upper region comprises at least two of the conductive tiers and that comprise upper select gates. Individual of the insulative tiers in the upper region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being solid. Other embodiments, including method, are disclosed.

First claim

The invention claimed is:

1 . A method used in forming a memory array comprising strings of memory cells, comprising:
forming a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier, channel-material strings extending through the insulative tiers and the conductive tiers and that directly electrically couple with conductor material of the conductor tier, the vertical stack comprising a memory-cell region comprising memory cells, individual of the insulative tiers in the memory-cell region comprising sacrificial material; the vertical stack comprising at least one of (a), (b), and (c), where:
(a): an upper region directly above the memory-cell region comprising at least two of the conductive tiers, the at least two conductive tiers in the upper region comprising upper select gates, at least one of the insulative tiers in the upper region comprising insulating material that is of different composition from that of the sacrificial material, the insulating material being directly above and directly below immediately-vertically-adjacent of the upper select gates;
(b): a lower region directly below the memory-cell region and directly above the conductor tier, the lower region comprising at least two of the conductive tiers, the at least two conductive tiers in the lower region comprising lower select gates, at least one of the insulative tiers in the lower region comprising insulator material that is of different composition from that of the sacrificial material, the insulator material being directly above and directly below immediately-vertically-adjacent of the lower select gates; and
(c): a dummy region in the memory-cell region comprising at least two of the conductive tiers and that comprise dummy wordlines, at least one of the insulative tiers in the dummy region comprising insulative material that is of different composition from that of the sacrificial material, the insulative material being directly above and directly below immediately-vertically-adjacent of the dummy wordlines; and
etching the sacrificial material in the memory-cell region selectively relative to the insulating, insulator, or insulative material of the at least one of the (a), the (b), or the (c), respectively, to form void space between immediately-adjacent of the conductive tiers in the memory-cell region and to not form void space between the at least two conductive tiers of said at least one of the (a), the (b), or the (c).

2 . The method of claim 1 wherein the vertical stack comprises only one of the (a), the (b), and the (c).

3 . The method of claim 1 wherein the vertical stack comprises at least two of the (a), the (b), and the (c).

4 . The method of claim 1 wherein the vertical stack comprises all three of the (a), the (b), and the (c).

5 . The method of claim 1 wherein the vertical stack comprises the (a).

6 . The method of claim 1 wherein the vertical stack comprises the (b).

7 . The method of claim 1 wherein the vertical stack comprises the (c).

8 . The method of claim 1 wherein the insulating, insulator, or insulative material of the at least one of the (a), the (b), or the (c), respectively, comprises a silicon oxide containing carbon and the sacrificial material comprises silicon dioxide.

9 . The method of claim 8 wherein the carbon is present at 100 ppm to 25 atomic percent of total of the silicon oxide and the carbon.

10 . The method of claim 9 wherein the carbon is present at 0.1 atomic percent to 15 atomic percent of the total of the silicon oxide and the carbon.

11 . The method of claim 10 wherein the carbon is present at 2 atomic percent to 12 atomic percent of the total of the silicon oxide and the carbon.

12 . The method of claim 1 wherein,
at least some of the conductive tiers in the memory-cell region initially comprise sacrifice material that is of different composition from that of the sacrificial material and from that of the at least one of the insulating, insulator, or insulative material of the at least one of the (a), the (b), or the (c), respectively; and
replacing the sacrifice material with conductive material prior to said etching.

Assignees

• Micron Technology Inc

Inventors

• Surthi Shyam
• Hill Richard J

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/30

  characterised by the memory core region · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title