Semiconductor structure and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-12557272-B2
Application number	US-202318177076-A
Country	US
Kind code	B2
Filing date	Mar 1, 2023
Priority date	Aug 25, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, which isolate a plurality of active areas extending in first direction in the substrate, in which a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in second direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a substrate, wherein a plurality of active areas arranged at intervals are provided in the substrate, wherein the active areas extend in a first direction; a plurality of bit lines arranged at intervals in parallel at the lower parts of the active areas, wherein an air gap is provided between adjacent bit lines; a plurality of gate word lines located above the bit lines, wherein the plurality of gate word lines are arranged in parallel at intervals in a second direction, wherein the second direction intersects with the first direction; an insulating isolation structure located between adjacent gate word lines, and between a gate word line and a bit line; a columnar structure located in an active area, wherein a bottom of the columnar structure is in contact with the bit line, and a top of the columnar structure penetrates through the gate word line and extends above the gate word line; a source located in the columnar structure and between the gate word line and the bit line; a drain located in the columnar structure and above the gate word line; and a conductive channel located in the columnar structure and between the source and the drain, wherein the gate word line is located at a periphery of the conductive channel.

2 . The semiconductor structure according to claim 1 , further comprising: a gate dielectric layer located between the conductive channel and the gate word line.

3 . The semiconductor structure according to claim 1 , wherein a material of the gate word lines is titanium nitride.

4 . The semiconductor structure according to claim 1 , further comprising:
a storage node contact structure located above the columnar structure and being in contact with and connected with the drain; and a storage capacitor located above the storage node contact structure and being in contact with and connected with the storage node contact structure.

5 . The semiconductor structure according to claim 1 , wherein a material of the bit lines is cobalt silicide.

Assignees

• Changxin Memory Tech Inc
• Beijing Superstring Academy Of Memory Tech

Inventors

• Shao Guangsu
• Xiao Deyuan
• Bai Weiping
• Qiu Yunsong

Classifications

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10B12/488

  Word lines · CPC title