Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Patent metadata

Field	Value
Publication number	US-12554494-B2
Application number	US-202418626629-A
Country	US
Kind code	B2
Filing date	Apr 4, 2024
Priority date	Jan 31, 2020
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

First claim

What is claimed is:

1 . A hardware processor comprising:
a plurality of logical processors; circuitry to provide a plurality of software thread runtime prediction histories for the plurality of logical processors; a decoder to decode a single instruction into a decoded single instruction, the single instruction having an operand; and an execution circuit to execute the decoded single instruction to reset at least one software thread runtime prediction history, of a logical processor that executes the single instruction, of the plurality of software thread runtime prediction histories of the circuitry according to a value from the operand.

2 . The hardware processor of claim 1 , further comprising a control register, wherein the execution circuit is to generate a general protection fault when any set bit of the value from the operand does not have a corresponding set bit in the control register.

3 . The hardware processor of claim 1 , wherein when the value from the operand is zero, the execution circuit is to execute the decoded single instruction as a no-operation.

4 . The hardware processor of claim 1 , wherein the execution circuit is to execute the decoded single instruction to reset the at least one software thread runtime prediction history only when the single instruction is requested for execution at a privilege level of zero.

5 . The hardware processor of claim 1 , wherein any attempt to execute the single instruction inside a transactional region results in a transaction abort.

6 . The hardware processor of claim 1 , wherein the single instruction comprises a value, of an explicit immediate operand, that is ignored.

7 . The hardware processor of claim 1 , wherein the plurality of software thread runtime prediction histories comprise a software thread runtime prediction history for each of a plurality of classes for each logical processor of the plurality of logical processors.

8 . The hardware processor of claim 7 , wherein the plurality of logical processors are implemented on a plurality of hardware cores.

9 . The hardware processor of claim 1 , wherein the operand is an implicit operand.

10 . A system comprising:
a system memory; a plurality of logical processors; circuitry to provide a plurality of software thread runtime prediction histories, in the system memory, for the plurality of logical processors; a decoder to decode a single instruction into a decoded single instruction, the single instruction having an operand; and an execution circuit to execute the decoded single instruction to reset at least one software thread runtime prediction history, of a logical processor that executes the single instruction, of the plurality of software thread runtime prediction histories of the circuitry according to a value from the operand.

11 . The system of claim 10 , further comprising a control register, wherein the execution circuit is to generate a general protection fault when any set bit of the value from the operand does not have a corresponding set bit in the control register.

12 . The system of claim 10 , wherein when the value from the operand is zero, the execution circuit is to execute the decoded single instruction as a no-operation.

13 . The system of claim 10 , wherein the execution circuit is to execute the decoded single instruction to reset the at least one software thread runtime prediction history only when the single instruction is requested for execution at a privilege level of zero.

14 . The system of claim 10 , wherein any attempt to execute the single instruction inside a transactional region results in a transaction abort.

15 . The system of claim 10 , wherein the single instruction comprises a value, of an explicit immediate operand, that is ignored.

16 . The system of claim 10 , wherein the plurality of software thread runtime prediction histories comprise a software thread runtime prediction history for each of a plurality of classes for each logical processor of the plurality of logical processors.

17 . The system of claim 16 , wherein the plurality of logical processors are implemented on a plurality of hardware cores.

18 . The system of claim 10 , wherein the operand is an implicit operand.

19 . A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction into a decoded single instruction with a decoder of a processor, the single instruction having an operand and the processor comprising a plurality of logical processors, and circuitry to provide a plurality of software thread runtime prediction histories for the plurality of logical processors; and executing the decoded single instruction with an execution circuit of the processor to reset at least one software thread runtime prediction history, of a logical processor that executes the single instruction, of the plurality of software thread runtime prediction histories of the circuitry according to a value from the operand.

20 . The non-transitory machine readable medium of claim 19 , wherein the processor further comprises a control register, and the executing generates a general protection fault when any set bit of the value from the operand does not have a corresponding set bit in the control register.

Assignees

• Intel Corp

Inventors

• Weissmann Eliezer
• Charney Mark
• Mishaeli Michael
• Valentine Robert
• Ravid Itai
• Brandt Jason W
• Neiger Gilbert
• Chaikin Baruch
• Rotem Efraim

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30101

  Special purpose registers · CPC title