Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Patent metadata

Field	Value
Publication number	US-11436018-B2
Application number	US-202017124813-A
Country	US
Kind code	B2
Filing date	Dec 17, 2020
Priority date	Jan 31, 2020
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

First claim

What is claimed is:

1. A hardware processor comprising:
a hardware guide scheduler comprising a plurality of software thread runtime property histories;
a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a control register; and
an execution circuit to execute the decoded single instruction to:
check that an enable bit of the control register is set, and
when the enable bit is set, reset the plurality of software thread runtime property histories of the hardware guide scheduler.

2. The hardware processor of claim 1 , wherein, when the enable bit is set, the execution circuit is to execute the decoded single instruction to reset the plurality of software thread runtime property histories of the hardware guide scheduler without modifying other architectural state of the hardware processor.

3. The hardware processor of claim 1 , wherein an opcode of the single instruction is a legacy opcode, and when the enable bit is not set, the execution circuit is to execute the decoded single instruction as a no-operation.

4. The hardware processor of claim 1 , wherein, when the enable bit is set, the execution circuit is to execute the decoded single instruction to reset the plurality of software thread runtime property histories of the hardware guide scheduler only when the single instruction is requested for execution by an operating system.

5. The hardware processor of claim 1 , wherein the plurality of software thread runtime property histories comprises a plurality of weights for respective classes of performance monitoring events for a plurality of cores of the hardware processor.

6. The hardware processor of claim 5 , wherein the respective classes comprise a first class for a first type of core and a second class for a second, higher performance core.

7. The hardware processor of claim 5 , wherein the respective classes comprise a first class for an integer type of vector instruction and a second class for a floating-point type of vector instruction.

8. The hardware processor of claim 1 , wherein the hardware guide scheduler is to store a hint for a next software thread that is to be executed on the hardware processor, in a register of the hardware processor to indicate to an operating system a core type of a plurality of cores types of the hardware processor, and the hint is based on the plurality of software thread runtime property histories.

9. A method comprising:
generating a plurality of software thread runtime property histories with a hardware guide scheduler of a hardware processor;
decoding a single instruction into a decoded single instruction with a decoder of the hardware processor, the single instruction having a field that identifies a control register; and
executing the decoded single instruction with an execution circuit of the hardware processor to:
check that an enable bit of the control register is set, and
when the enable bit is set, reset the plurality of software thread runtime property histories of the hardware guide scheduler.

10. The method of claim 9 , wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler without modifying other architectural state of the hardware processor.

11. The method of claim 9 , wherein an opcode of the single instruction is a legacy opcode, and when the enable bit is not set, the execution circuit executes the decoded single instruction as a no-operation.

12. The method of claim 9 , wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler only when the single instruction is requested for execution by an operating system.

13. The method of claim 9 , wherein the plurality of software thread runtime property histories comprises a plurality of weights for respective classes of performance monitoring events for a plurality of cores of the hardware processor.

14. The method of claim 13 , wherein the respective classes comprise a first class for a first type of core and a second class for a second, higher performance core.

15. The method of claim 13 , wherein the respective classes comprise a first class for an integer type of vector instruction and a second class for a floating-point type of vector instruction.

16. The method of claim 9 , further comprising storing a hint, by the hardware guide scheduler, for a next software thread that is to be executed on the hardware processor, in a register of the hardware processor to indicate to an operating system a core type of a plurality of cores types of the hardware processor, and the hint is based on the plurality of software thread runtime property histories.

17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction into a decoded single instruction with a decoder of a hardware processor, the single instruction having a field that identifies a control register; and
executing the decoded single instruction with an execution circuit of the hardware processor to:
check that an enable bit of the control register is set, and
when the enable bit is set, reset a plurality of software thread runtime property histories of a hardware guide scheduler of the hardware processor.

18. The non-transitory machine readable medium of claim 17 , wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler without modifying other architectural state of the hardware processor.

19. The non-transitory machine readable medium of claim 17 , wherein an opcode of the single instruction is a legacy opcode, and when the enable bit is not set, the execution circuit executes the decoded single instruction as a no-operation.

20. The non-transitory machine readable medium of claim 17 , wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler only when the single instruction is requested for execution by an operating system.

21. The non-transitory machine readable medium of claim 17 , wherein the plurality of software thread runtime property histories comprises a plurality of weights for respective classes of performance monitoring events for a plurality of cores of the hardware processor.

22. The non-transitory machine readable medium of claim 21 , wherein the respective classes comprise a first class for a first type of core and a second class for a second, higher performance core.

23. The non-transitory machine readable medium of claim 21 , wherein the respective classes comprise a first class for an integer type of vector instruction and a second class for a floating-point type of vector instruction.

24. The non-transitory machine readable medium of claim 17 , wherein the method further comprises storing a hint, by the hardware guide scheduler, for a next software thread that is to be executed on the hardware processor, in a register of the hardware processor to indicate to an operating system a core type of a plurality of cores types of the hardware processor, and the hint is based on the plurali

Assignees

• Intel Corp

Inventors

• Weissmann Eliezer
• Charney Mark
• Mishaeli Michael
• Valentine Robert
• Ravid Itai
• Brandt Jason W
• Neiger Gilbert
• Chaikin Baruch
• Rotem Efraim

Classifications

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/3844 Primary

  using dynamic branch prediction, e.g. using branch history tables · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title