Sharing TLB mappings between contexts

Patent metadata

Field	Value
Publication number	US-9703566-B2
Application number	US-201113997789-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.

First claim

What is claimed is:

1. A processor comprising:
a translation lookaside buffer (TLB) to include an entry containing shared mapping information including a mapping of a virtual address to a physical address and one or more attributes associated with a context of a first thread and a context of a second thread; and
a control logic circuit to:
compare a physical address and one or more attributes corresponding to a mapping request for an input virtual address to the physical address and the one or more attributes in the entry of the TLB, and
allocate a new entry in the TLB if at least one of:
the physical address corresponding to the mapping request for the input virtual address does not match the physical address in the entry, or
the one or more attributes corresponding to the mapping request for the input virtual address do not match the one or more attributes in the entry, wherein the one or more attributes in the entry comprise user/supervisor access permissions.

2. The processor as recited in claim 1 further comprising a plurality of registers, the context of the first thread comprising a first hardware context to include one or more first registers of the plurality of registers allocated to the first thread, and the context of the second thread comprising a second hardware context to include one or more second registers of the plurality of registers allocated to the second thread.

3. The processor as recited in claim 1 in which at least the first thread and the second thread are to execute on the processor contemporaneously.

4. The processor as recited in claim 1 , the control logic circuit further comprising a logic circuit to request fetching of new mapping information in response to the mapping request if none of the contexts stored in the entry of the TLB match a context corresponding to the mapping request.

5. The processor as recited in claim 1 , the control logic circuit further comprising a logic circuit to, if none of the contexts stored in the entry of the TLB match a context corresponding to the mapping request, add the context corresponding to the mapping request to the entry if the physical address corresponding to the mapping for the input virtual address matches the physical address in the entry, and the one or more attributes corresponding to the mapping request for the input virtual address match the one or more attributes in the entry.

6. The processor as recited in claim 1 in which the processor includes multiple processor cores, the TLB and the control logic circuit corresponding to a first processor core of the multiple processor cores, the first thread and the second thread to execute on respective first and second logical processors provided by the first processor core.

7. A processor comprising:
a data structure to include an entry containing first mapping information having a mapping of a virtual address to a physical address, one or more attributes, and a first context associated with a first thread; and
a control logic circuit to:
receive a mapping request that includes a virtual address and a second context associated with a second thread, and
when the virtual address in the entry matches the virtual address of the mapping request and the second context does not match the first context:
to allocate a new entry in the data structure if at least one of:
a physical address corresponding to the virtual address of the mapping request does not match the physical address in the entry, or
 one or more attributes corresponding to the mapping request do not match the one or more attributes in the entry, and

to add the second context to the first mapping information contained in the entry if the physical address corresponding to the virtual address of the mapping request matches the physical address in the entry, and the one or more attributes corresponding to the mapping request match the one or more attributes in the entry, wherein the one or more attributes in the entry comprise user/supervisor access permissions.

8. The processor as recited in claim 7 , the control logic circuit further comprising a logic circuit to respond to the mapping request with the physical address in the entry when the virtual address in the entry matches the virtual address of the mapping request and the second context matches the first context.

9. The processor as recited in claim 7 , wherein the one or more attributes in the entry comprises at least one of an access permission attribute, a processing privilege attribute, a page attribute, and a memory location attribute.

10. The processor as recited in claim 7 , the control logic circuit further comprising a logic circuit to, when the virtual address in the entry does not match the virtual address of the mapping request, allocate a new entry in the data structure.

11. The processor as recited in claim 7 further comprising a plurality of registers, the first context comprising a first hardware context to include one or more first registers of the plurality of registers allocated to the first thread, and the second context comprising a second hardware context to include one or more second registers of the plurality of registers allocated to the second thread.

12. The processor as recited in claim 7 in which the data structure is a translation lookaside buffer (TLB) and the processor includes multiple processor cores, the TLB and the control logic circuit corresponding to a first processor core of the multiple processor cores.

13. A method comprising:
maintaining first mapping information associated with a first context in an entry of a data structure, the first mapping information including a mapping of a first virtual address to a first physical address and one or more attributes;
receiving a request for second mapping information associated with a second context, the second mapping information including a mapping of the first virtual address to a second physical address and one or more attributes;
comparing the first mapping information with the second mapping information; and
allocating a new entry in the data structure if at least one of:
the first physical address does not match the second physical address, or
the one or more attributes of the first mapping information do not match the one or more attributes of the second mapping information, wherein the one or more attributes in the entry comprise user/supervisor access permissions.

14. The method as recited in claim 13 further comprising:
receiving a subsequent request for mapping information including the first virtual address and the first context; and
returning the first physical address.

15. The method as recited in claim 13 further comprising, prior to the comparing, fetching the second mapping information from one or more page tables in response to the request for second mapping information.

16. The method as recited in claim 13 further comprising adding the second context to the first mapping information if the first physical address matches the second physical address, and the one or more attributes of the first mapping information match the one or more attributes of the second mapping information.

17. The method as recited in claim 13 wherein the first context is a hardware context associated with a first thread of execution to execute on a processor and the second context is a second hardware context associated with a second thread of execution to execute on the processor contemporaneously with the first thread.

18. A system comprising:
a processor;
a memory to maintain a translation lookaside buffer (TLB),

Assignees

• Combs Jonathan D
• Brandt Jason W
• Chaffin Benjamin C
• Gago Julio
• Intel Corp

Inventors

• Combs Jonathan D
• Brandt Jason W
• Chaffin Benjamin C
• Gago Julio
• Glew Andrew F

Classifications

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F9/3814 Primary

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F2212/1024

  Latency reduction · CPC title