Semiconductor package with stiffener structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12550775-B2
Application number	US-202418789496-A
Country	US
Kind code	B2
Filing date	Jul 30, 2024
Priority date	May 6, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A semiconductor package includes a first component, a second component, and a stiffener rib. The first component is disposed on a substrate. The second component is disposed aside the first component and on the substrate. The stiffener rib is disposed between the first component and the second component. The lid is attached to the stiffener rib, the first component and the second component. The lid includes a recess portion on the stiffener rib. A first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib. A first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a first component, disposed on a substrate; a second component, disposed aside the first component and on the substrate; a stiffener rib between the first component and the second component; a lid, attached to the stiffener rib, the first component and the second component, wherein the lid comprises a recess portion on the stiffener rib, wherein a first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib, and wherein a first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.

2 . The semiconductor package of claim 1 , wherein the stiffener rib has a top surface area and a bottom surface area, and the top surface area is greater than the bottom surface area.

3 . The semiconductor package of claim 1 , wherein a middle width of the stiffener rib is greater than a top width of the stiffener rib and a bottom width of the stiffener rib.

4 . The semiconductor package of claim 1 , wherein a first bottom space between a first bottom sidewall of the stiffener rib and a first sidewall of the first component is greater than a second bottom space between a bottom sidewall of the stiffener rib and a second sidewall of the second component.

5 . The semiconductor package of claim 4 , wherein a width of the first bottom space is greater than a width of the first top space, and a width of the second bottom space is greater than a width of the second top space.

6 . The semiconductor package of claim 5 , further comprising a third component disposed in the first bottom space.

7 . The semiconductor package of claim 1 , wherein a height of the stiffener rib is greater than a height of the first component and a height of the second component.

8 . The semiconductor package of claim 1 , wherein the lid is attached to the first component through a first thermal interface material (TIM), the lid is attached to the second component through a second thermal interface material, and the lid is attached to the stiffener rib through an adhesive.

9 . The semiconductor package of claim 8 , wherein the adhesive is higher than the first thermal interface material and the second thermal interface material.

10 . A semiconductor package, comprising:
a first component and a plurality of second components, disposed on and electrically connected to a substrate; a stiffener structure, adhered to the substrate, the stiffener structure comprising:
a pair of stiffener ribs disposed between the first component and one of the plurality of second components, and the first component and another one of the plurality of second components; and
a lid comprising:
a first portion attached to the first component;
a plurality of second portions attached to the plurality of second components; and
a plurality of third portions attached to the pair of stiffener ribs,
wherein a bottom of the third portions is higher than a bottom of the first portion and bottoms of the plurality of second portions, and sidewalls of the first portion and the plurality of second portions surround the pair of stiffener ribs.

11 . The semiconductor package of claim 10 , wherein each of the pair of stiffener ribs comprises a top part and a bottom part, and a width of top part is greater than a width of the bottom part.

12 . The semiconductor package of claim 11 , wherein one the pair of stiffener ribs is positioned offset from a center line of a corresponding third portion.

13 . The semiconductor package of claim 11 , wherein a distance between a first sidewall of the bottom part and a sidewall of the first component adjacent the bottom part is greater than a distance between a second sidewall of the bottom part and a sidewall of one of the plurality of the second components adjacent the bottom part.

14 . The semiconductor package of claim 13 , further comprising: a third component disposed between the bottom part and the first component.

15 . The semiconductor package of claim 14 , wherein a top surface of the third component is lower than a bottom surface of the top part.

16 . The semiconductor package of claim 10 , wherein the stiffener structure further comprises:
a stiffener ring extending along a perimeter of the substrate and surrounding the first component and the plurality of second components, and connected to the pair of stiffener ribs, wherein a top surface of the stiffener ring is lower than top surfaces of the pair of stiffener ribs.

17 . A method of manufacturing a semiconductor package, comprising:
bonding a first component on a substrate; bonding a second component on the substrate and aside the first component; adhering a stiffener rib between the first component and the second component; attaching a lid to the stiffener rib, the first component and the second component, wherein the lid comprises a recess portion on the stiffener rib, wherein a first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib, and wherein a first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.

18 . The method of claim 17 , wherein
a height of the stiffener rib is greater than a height of the first component and a height of the second component, and the stiffener rib has a top surface area and a bottom surface area, and the top surface area is greater than the bottom surface area.

19 . The method of claim 17 , wherein a first bottom space between a first bottom sidewall of the stiffener rib and a first sidewall of the first component is different from a second bottom space between a bottom sidewall of the stiffener rib and a second sidewall of the second component.

20 . The method of claim 18 , wherein the lid is attached to the first component through a first thermal interface material (TIM), the lid is attached to the second component through a second thermal interface material, and the lid is attached to the stiffener rib through an adhesive,
wherein the adhesive is higher than the first thermal interface material and the second thermal interface material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Wensen
• Tsai Yu-Ling
• Chiu Chien-Chia
• Chen Tsung-Yu

Classifications

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title