Array substrate and display device

Patent metadata

Field	Value
Publication number	US-12550446-B2
Application number	US-202218276646-A
Country	US
Kind code	B2
Filing date	Jul 14, 2022
Priority date	Jul 14, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

Provided is an array substrate, including: a substrate; a first insulating layer and a second insulating layer that are successively stacked; a first electrode disposed on a side, proximal to the substrate, of the first insulating layer; a second electrode disposed between the first insulating layer and the second insulating layer; and a lap electrode disposed on a side, distal from the substrate, of the second insulating layer. The array substrate includes a plurality of first vias and a plurality of second vias. The lap electrode is electrically connected to the first electrode and is electrically connected to the second electrode. An orthographic projection of the first electrode on the substrate is overlapped with an orthographic projection of the second electrode on the substrate, and covers a region between at least one of the first vias and at least one of the second vias.

First claim

What is claimed is:

1 . An array substrate, comprising:
a substrate; a first insulating layer and a second insulating layer that are successively stacked along a direction perpendicular to and away from the substrate; a first electrode disposed on a side, proximal to the substrate, of the first insulating layer; a second electrode disposed between the first insulating layer and the second insulating layer; and a lap electrode disposed on a side, distal from the substrate, of the second insulating layer; wherein
the array substrate comprises a plurality of first vias and a plurality of second vias, and the lap electrode is electrically connected to the first electrode through the plurality of first vias and is electrically connected to the second electrode through the plurality of second vias; and
an orthographic projection of the first electrode on the substrate is at least partially overlapped with an orthographic projection of the second electrode on the substrate, and the orthographic projection of the first electrode on the substrate covers a region between at least one of the first vias and at least one of the second vias,
wherein the first electrode comprises a first electrode strip and a second electrode strip that are arranged in parallel, and at least one first connection arm disposed between the first electrode strip and the second electrode strip; and
orthographic projections of the plurality of first vias on the substrate are within an orthographic projection of the first electrode strip on the substrate, and orthographic projections of at least a portion of the plurality of second vias on the substrate are within an orthographic projection of the second electrode strip on the substrate and are within the orthographic projection of the second electrode on the substrate.

2 . The array substrate according to claim 1 , wherein an orthographic projection of the first connection arm on the substrate covers an entire region between a first target via and a second target via;
wherein the first target via is any of the plurality of first vias, and the second target via is one of the plurality of second vias, of which an orthographic projection is overlapped with the second electrode strip and which is adjacent to the first target via.

3 . The array substrate according to claim 1 , wherein the plurality of second vias comprise at least one first lap via and a plurality of second lap vias, and the second electrode comprises a second electrode body and at least one second connection arm corresponding to the at least one first lap via one by one, wherein the second connection arm is electrically connected to the second electrode body; wherein
an orthographic projection of the at least one first lap via on the substrate is within the orthographic projection of the first electrode strip on the substrate and is within an orthographic projection of a corresponding second connection arm on the substrate; and orthographic projections of the plurality of second lap vias on the substrate are within the orthographic projection of the second electrode strip on the substrate and are within an orthographic projection of the second electrode body on the substrate.

4 . The array substrate according to claim 3 , wherein
the plurality of first vias are arranged in at least one row, and one of the first lap vias is disposed between adjacent two first vias in a row of the first vias; and the plurality of second lap vias are arranged in at least one row.

5 . The array substrate according to claim 3 , wherein in a case a plurality of the first connection arms and a plurality of the second connection arms are provided, the plurality of the first connection arms and the plurality of the second connection arms are alternately arranged one by one, and a gap is present between one of the first connection arms and one of the second connection arm that are adjacent.

6 . The array substrate according to claim 3 , wherein a boundary of an orthographic projection of the first connection arm on the substrate is overlapped with a boundary of an orthographic projection of the second connection arm on the substrate.

7 . A display device, comprising: an array substrate and a color film substrate that are disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the color film substrate;
wherein the array substrate comprises:
a substrate;
a first insulating layer and a second insulating layer that are successively stacked along a direction perpendicular to and away from the substrate;
a first electrode disposed on a side, proximal to the substrate, of the first insulating layer;
a second electrode disposed between the first insulating layer and the second insulating layer; and
a lap electrode disposed on a side, distal from the substrate, of the second insulating layer; wherein
the array substrate comprises a plurality of first vias and a plurality of second vias, and the lap electrode is electrically connected to the first electrode through the plurality of first vias and is electrically connected to the second electrode through the plurality of second vias; and

an orthographic projection of the first electrode on the substrate is at least partially overlapped with an orthographic projection of the second electrode on the substrate, and the orthographic projection of the first electrode on the substrate covers a region between at least one of the first vias and at least one of the second vias,
wherein the first electrode comprises a first electrode strip and a second electrode strip that are arranged in parallel, and at least one first connection arm disposed between the first electrode strip and the second electrode strip; and orthographic projections of the plurality of first vias on the substrate are within an orthographic projection of the first electrode strip on the substrate, and orthographic projections of at least a portion of the plurality of second vias on the substrate are within an orthographic projection of the second electrode strip on the substrate and are within the orthographic projection of the second electrode on the substrate.

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Quanzhou
• Qian Haijiao
• Chen Liang
• Liu Zexu

Classifications

• G02F1/133514

  Colour filters · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• G02F1/13629 Primary

  Multilayer wirings · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title