Array Substrate, Display Panel and Method for Manufacturing Array Substrate

Patent metadata

Field	Value
Publication number	US-2016358947-A1
Application number	US-201615163805-A
Country	US
Kind code	A1
Filing date	May 25, 2016
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

An array substrate is disclosed, which includes a connection structure of a second short-circuit ring and one corresponding data line, and this connection structure includes: a first electrode disposed on a base substrate; a connection line disposed on the first electrode; a first insulating layer disposed on the first electrode and the connection line, in which the data line connected with the second short-circuit ring is disposed on the first insulating layer; a second insulating layer disposed on the data line connected with the second short-circuit ring; and a second electrode disposed on the second insulating layer, in which the second electrode is connected with the data line connected with the second short-circuit ring through a first via hole and connected with the first electrode through a second via hole.

First claim

What is claimed is:

1 . An array substrate, comprising:
a group of data lines and a group of gate lines which are intercrossed with each other; and a first short-circuit ring and a second short-circuit ring which are disposed along a peripheral area of the array substrate, wherein two adjacent data lines in the group of data lines are respectively connected with the first short-circuit ring and the second short-circuit ring; and a connection structure between the second short-circuit ring and one corresponding data line comprises:
a first electrode disposed on a base substrate;
a connection line disposed on the first electrode;
a first insulating layer disposed on the first electrode and the connection line, in which the data line connected with the second short-circuit ring is disposed on the first insulating layer;
a second insulating layer disposed on the data line connected with the second short-circuit ring, in which the second insulating layer is provided with a first via hole on the data line connected with the second short-circuit ring, and the first insulating layer and the second insulating layer are provided with a second via hole on the first electrode; and
a second electrode disposed on the second insulating layer, in which the second electrode is connected with the data line connected with the second short-circuit ring through the first via hole and connected with the first electrode through the second via hole.

2 . The array substrate according to claim 1 , wherein the first short-circuit ring and the group of data lines are arranged in the same layer; and/or the second short-circuit ring and the group of gate lines are arranged in the same layer.

3 . The array substrate according to claim 1 , wherein the first electrode is a first transparent electrode; and/or the second electrode is a second transparent electrode.

4 . The array substrate according to claim 1 , wherein the connection line is a gate connection line that is disposed in a same layer as the gate lines.

5 . The array substrate according to claim 1 , wherein the first short-circuit ring is connected with the data lines in odd numbered sequence in the group of the data lines, and the second short-circuit ring is connected with the data lines in even numbered sequence in the group of the data lines; or
the first short-circuit ring is connected with the data lines in even numbered sequence in the group of the data lines, and the second short-circuit ring is connected with the data lines in odd numbered sequence in the group of the data lines.

6 . The array substrate according to claim 1 , wherein the array substrate is an advanced super dimension switch (ADS) mode array substrate and comprises a plate electrode and a slit electrode; the first electrode and the plate electrode are arranged in the same layer; and the second transparent electrode and the slit electrode of the array substrate are arranged in the same layer.

7 . The array substrate according to claim 1 , wherein the connection line is connected with the second short-circuit ring.

8 . A display panel, comprising the array substrate according to claim 1 .

9 . A method for manufacturing an array substrate, comprising:
forming data lines and a first short-circuit ring on a base substrate, in which the data lines in odd numbered sequence or the data lines in even numbered sequence are connected with the first short-circuit ring; forming a first electrode, a connection line and a second short-circuit ring on the base substrate, in which the connection line is disposed on the first electrode and connected with the second short-circuit ring and the first electrode; forming a first insulating layer on a layer structure of the connection line and the second short-circuit ring, in which the data lines and the first short-circuit ring are formed on the first insulating layer; forming a second insulating layer on a layer structure of the data lines and the first short-circuit ring, in which the second insulating layer is provided with a first via hole on the data line not connected with the first short-circuit ring, and the first insulating layer and the second insulating layer are provided with a second via hole on the first electrode; and forming a second electrode on the second insulating layer, in which the second electrode is connected with one corresponding data line through the first via hole and connected with the first electrode through the second via hole.

10 . The method according to claim 9 , wherein the connection line is lapped over an upper surface of the first electrode.

11 . The method according to claim 9 , wherein the first electrode is a first transparent electrode; and/or the second electrode is a second transparent electrode.

12 . The method according to claim 9 , wherein the connection line is a gate connection line.

13 . The method according to claim 9 , further comprising:
forming plate electrodes arranged in the same layer as the first electrode in the process of forming the first electrode; and forming slit electrodes arranged in the same layer as the second electrode in the process of forming the second electrode.

14 . The method according to claim 9 , further comprising:
forming gate lines arranged in the same layer as the connection line and the second short-circuit ring in the process of forming the connection line and the second short-circuit ring.

15 . The method according to claim 9 , wherein
the first electrode, the connection line and the second short-circuit ring are formed by a half-tone mask patterning process.

16 . The method according to claim 9 , further comprising: forming a semiconductor layer on the first insulating layer after forming the first insulating layer.

17 . The method according to claim 9 , further comprising:
forming plate electrodes arranged in the same layer as the first electrode in the process of forming the first electrode; forming gate lines arranged in the same layer as the connection line and the second short-circuit ring in the process of forming the connection line and the second short-circuit ring; forming a semiconductor layer on the first insulating layer after forming the first insulating layer; and forming slit electrodes arranged in the same layer as the second electrode in the process of forming the second electrode.

18 . The method according to claim 9 , wherein
the first electrode, the connection line and the second short-circuit ring are formed by a half-tone mask patterning process.

19 . The method according to claim 9 , wherein
the semiconductor layer, the data lines and the first short-circuit ring are formed by a half-tone mask patterning process.

20 . An array substrate, comprising:
a group of data lines; and a first short-circuit ring and a second short-circuit ring which are disposed along a peripheral area of the array substrate, wherein in the group of data lines, the first data line in two adjacent data lines is connected with the first short-circuit ring, and the second data line in the two adjacent data lines is connected with the second short-circuit ring; and a connection structure of the second short-circuit ring and the second data line comprises:
a first electrode disposed on a base substrate;
a first part to be connected disposed on the first electrode and connected with the first electrode;
a first insulating layer disposed on the first electrode and the first part to be connected; and
a second part to be connected dispo

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Cai Zhenfei
• Fang Juan
• Wei Xiaomei
• Chen Min

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/1244 Primary

  Electricity · mapped topic