Array substrate and display device

Patent metadata

Field	Value
Publication number	US-2021210521-A1
Application number	US-201816077527-A
Country	US
Kind code	A1
Filing date	Feb 8, 2018
Priority date	Jul 17, 2017
Publication date	Jul 8, 2021
Grant date	—

Abstract

The present disclosure provides an array substrate, which includes a first signal line and a second signal line arranged on a substrate as different layers that are insulating and spaced apart from each other, wherein one end of the first signal line includes a first conductive section, one end of the second signal line includes a second conductive section, the first conductive section and the second conductive section are electrically connected through a connecting structure, and wherein orthographic projections of an area where the first conductive section is located and an area where the second conductive section is located overlap at least partially. The array substrate can reduce the possibility of occurrence of circuit break between signal lines and improve the effect of connection between different signal lines.

First claim

1 . An array substrate; comprising a first signal line and a second signal line arranged on a substrate as different layers that are insulating and spaced apart from each other, wherein one end of the first signal line comprises a first conductive section, one end of the second signal line comprises a second conductive section, the first conductive section and the second conductive section are electrically connected through a connecting structure, and wherein orthographic projections of an area where the first conductive section is located and an area where the second conductive section is located overlap at least partially.

2 . The array substrate according to claim 1 , wherein the second conductive section is located at a side of the first conductive section facing away from the substrate, an insulating layer is arranged between a layer where the first conductive section is located and a layer where the second conductive section is located, and a passivation layer is arranged on a side of the second conductive section facing away from the substrate; and
wherein, the connecting structure is connected to the first conductive section through at least one first via hole that penetrates both the passivation layer and the insulating layer, and is connected to the second conductive section through at least one second via hole that penetrates the passivation layer.

3 . The array substrate according to claim 2 , wherein there are a plurality of first via holes and second via holes, and the plurality of first via holes correspond one to one to the plurality of second via holes.

4 . The array substrate according to claim 3 , wherein orthographic projections of the first conductive section and the second conductive section on the substrate overlap at least partially.

5 . The array substrate according to claim 4 , wherein an orthographic projection of each of the plurality of second via holes on the substrate is within the range of the orthographic projection of the second conductive section on the substrate, an orthographic projection of each of the plurality of first via holes on the substrate is outside of the range of the orthographic projection of the second conductive section on the substrate, and the orthographic projection of each first via hole is adjacent to but not overlapping with the orthographic projection of the corresponding second via hole.

6 . The array substrate according to claim 4 , wherein the second conductive section comprises at least one slit penetrating through it, an orthographic projection of at least one of the first via holes on the substrate is within the range of an orthographic projection of the at least one slit on the substrate, an orthographic projection of a second via hole corresponding to the at least one of the first via holes on the substrate is outside of the range of the orthographic projection of the at least one slit on the substrate, and the orthographic projection of each first via hole is adjacent to but not overlapping with the orthographic projection of the corresponding second via hole.

7 . The array substrate according to claim 6 , wherein the orthographic projection of each of the at least one slit on the substrate is a rectangle.

8 . The array substrate according to claim 6 , wherein the second conductive section comprises a plurality of slits penetrating through it, and orthographic projections of the plurality of slits on the substrate cover the orthographic projections of the plurality of first via holes on the substrate.

9 . The array substrate according to claim 2 , wherein the first conductive section comprises a first comb handle and a plurality of spaced first comb teeth are connected to the first comb handle, and the area where the first conductive section is located is the sum of an area where the first comb handle is located, an area where the plurality of first comb teeth are located and an area where intervals between the plurality of first comb teeth are located; and
the second conductive section comprises a second comb handle and a plurality of spaced second comb teeth are connected to the second comb handle, and the area where the second conductive section is located is the sum of an area where the second comb handle is located, an area where the plurality of second comb teeth are located and an area where intervals between the plurality of second comb teeth are located; wherein, orthographic projections of the plurality of first comb teeth on the substrate and orthographic projections of the plurality of second comb teeth on the substrate are distributed alternately, the orthographic projection of the at least one first via hole on the substrate is within the orthographic projections of the plurality of first comb teeth on the substrate, and the orthographic projection of the at least one second via hole on the substrate is within the orthographic projections of the plurality of second comb teeth on the substrate.

10 . The array substrate according to claim 1 , wherein the substrate comprises a display area and a non-display area surrounding the display area, and the first signal line, the first conductive section, the second signal line and the second conductive section are all arranged in the non-display area.

11 . The array substrate according to claim 10 , wherein the display area also includes gate lines and data lines that are arranged in different layers, and wherein the first signal line, the first conductive section and the gate lines are arranged in the same layer and made of the same material, and the second signal line, the second conductive section and the data lines are arranged in the same layer and made of the same material.

12 . The array substrate according to claim 11 , wherein the display area of the substrate further includes an electrode layer which is arranged at a side of the data lines facing away from the substrate, and the connecting structure and the electrode layer are arranged in the same layer and made of the same material.

13 . The array substrate according to claim 1 , wherein the connecting structure is made of a transparent conductive material.

14 . A display device comprising the array substrate according to claim 1 .

15 . The display device according to claim 14 , wherein the second conductive section is located at a side of the first conductive section facing away from the substrate, an insulating layer is arranged between a layer where the first conductive section is located and a layer where the second conductive section is located, and a passivation layer is arranged on a side of the second conductive section facing away from the substrate; and
wherein, the connecting structure is connected to the first conductive section through at least one first via hole that penetrates both the passivation layer and the insulating layer, and is connected to the second conductive section through at least one second via hole that penetrates the passivation layer.

16 . The display device according to claim 15 , wherein there are a plurality of first via holes and second via holes, and the plurality of first via holes are corresponding one to one to the plurality of second via holes one by one.

17 . The display device according to claim 16 , wherein orthographic projections of the first conductive section and the second conductive section on the substrate overlap at least partially.

18 . The display device according to claim 17 , wherein an orthographic projection of each of the plurality of second via holes on the substrate is within the range of the orthographic projec

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Li Lin
• Xu Yanbin

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title