Thin-film storage transistor with ferroelectric storage layer

Patent metadata

Field	Value
Publication number	US-12550382-B2
Application number	US-202217674137-A
Country	US
Kind code	B2
Filing date	Feb 17, 2022
Priority date	Jan 22, 2020
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (“FeFETs”), thereby providing a very high-speed, high-density memory array.

First claim

We claim:

1 . In a 3-dimensional array of memory strings formed above a planar surface of a semiconductor substrate, each memory string comprising:
first, second and third transistor material layers, the third transistor material layer being formed to be in contact with both the first and the second transistor material layers; a plurality of conductors; and a ferroelectric storage layer between the conductors and the third transistor material layer, and the third transistor material layer is provided between the ferroelectric storage layer and the first and second transistor material layers, wherein (i) the first, the second and the third transistor material layers, the ferroelectric storage layer and the conductors form a plurality of ferroelectric field-effect transistors (“FeFETs”) for the memory string; (ii) the first and the second transistor material layers provide a common bit line and a common source line for the FeFETs, respectively; (iii) the third transistor material layer provides a channel region for each FeFET in the memory string, (iv) the ferroelectric storage layer provides a polarizable layer for each FeFET; and (v) each conductor provides a gate electrode for one of the FeFETs in the memory string, wherein each memory string comprises the plurality of FeFETs formed along the common bit line and the common source line, each FeFET being formed at the intersection of each of the conductors to the common bit line and the common source line, and wherein the three dimensional array of memory strings comprises stacks of memory strings formed over the planar surface of the semiconductor substrate, the stacks of memory strings being arrange in a row along a first direction substantially parallel to the planar surface of the semiconductor substrate and each stack being separated from adjacent stacks of memory strings by isolation dielectric layers, the plurality of conductors associated with each memory string being provided in the isolation dielectric layer and extending in a second direction substantially normal to the planar surface of the semiconductor substrate to intersect with the memory strings in each stack, forming the FeFETs at each intersection with the common bit line and the common source line of each memory string in each stack.

2 . The memory string of claim 1 , wherein the first and second transistor material layers each comprise a semiconductor layer of a first conductivity type, and the third transistor material layer comprises a semiconductor layer of a second conductivity type opposite the first conductivity type.

3 . The memory string of claim 1 , wherein the first and second transistor material layers each comprise a metal layer, and the third transistor material layer comprises a conductive metal oxide.

4 . The memory string of claim 3 , wherein the metal layer comprises one or more of titanium nitride-lined tungsten, tungsten, cobalt, and molybdenum.

5 . The memory string of claim 3 , wherein the conductive metal oxide comprises one or more of: gallium oxides, zinc oxides, and indium oxides.

6 . The memory string of claim 5 , wherein the indium oxides comprise one or more of: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and any conductive metal oxides with charge-carriers mobilities modifiable by inclusion of one or more impurities.

7 . The memory string of claim 1 , wherein the FeFETs of the memory string are organized as a NOR memory string.

8 . The memory string of claim 1 , wherein the ferroelectric storage layer comprises an interface dielectric layer and a ferroelectric material layer.

9 . The memory string of claim 8 , wherein the interface dielectric layer comprises a material with a dielectric constant greater than 3.9.

10 . The memory string of claim 8 , wherein the interface dielectric layer comprises one or more of zirconium oxide (ZrO 2 ), silicon oxynitride (SiON), silicon nitride (Si 3 N 4 ), or silicon oxide (SiO 2 ).

11 . The memory string of claim 8 , wherein the interface dielectric layer is between 0.0 to 2.0 nm thick.

12 . The memory string of claim 8 , wherein the interface dielectric layer comprises a native oxide formed inherently when the ferroelectric material layer is directly deposited on the third semiconductor layer.

13 . The memory string of claim 8 , wherein the interface dielectric layer comprises silicon oxide (SiO 2 ) and a high-k dielectric material.

14 . The memory string of claim 13 , wherein the high-k dielectric material comprises zirconium oxide (ZrO 2 ).

15 . The memory string of claim 8 , wherein the ferroelectric material layer comprises a zirconium-doped hafnium oxide (HfO 2 :Zr; or “HZO”), an aluminum-doped hafnium oxide (HfO 2 :Al), a silicon-doped hafnium oxide (HfO 2 :Si) or a lanthanum-doped hafnium oxide (HfO 2 :La), or any combination thereof.

16 . The memory string of claim 15 , wherein the HZO comprises hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), any combination thereof, or any other hafnium oxide that includes zirconium impurities.

17 . The memory string of claim 8 , wherein the 3-dimensional array of memory strings are organized such that the ferroelectric material layer of each FeFET is separated from the ferroelectric material layer of the FeFETs in other memory strings.

18 . The memory string of claim 1 , wherein the ferroelectric storage layer is deposited on the third semiconductor layer using atomic layer deposition (ALD) techniques at temperature between 200° C. to 330° C.

19 . The memory string of claim 18 , wherein the temperature is between 270° C. and 330° C.

20 . The memory string of claim 18 , wherein the ferroelectric storage layer is subject to a post-deposition annealing step at a temperature between 400° C. and 1000° C.

21 . The memory string of claim 1 , wherein each conductor comprises tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), titanium (Ti), or any combination or alloy of thereof.

22 . The memory string of claim 1 , wherein each FeFET has a conducting state threshold voltage greater than 0.0 volts.

23 . The memory string of claim 22 , wherein the third transistor material layer is boron-doped.

24 . The memory string of claim 1 , wherein each FeFET has a 1.0 volts to 2.0 volts window between its threshold voltage in its conducting state and its threshold voltage in its non-conducting state.

25 . The memory string of claim 1 , wherein the third transistor material layer is floating during a programming operation wherein the programming operation is conducted in conjunction with voltage biases that provide a gate-induced drain leakage (GIDL) effect.

26 . The memory string of claim 1 , wherein at least a portion of the ferroelectric storage layer is deposited using a selective atomic layer deposition technique involving self-assembled monolayers (SAMs) acting on the isolation dielectric layers.

27 . The memory string of claim 1 , wherein the SAMs comprise species having hydroxyl terminations.

28 . The memory string of claim 1 , wherein the FeFETs of the memory string are arranged along the first direction substantially parallel to the planar surface.

29 . The memory string of claim 1 , wherein the FeFETs of a stack of memory strings are arranged along the second directi

Assignees

• Sunrise Memory Corp

Inventors

• Samachisa George
• Purayath Vinod
• Chien Wu-Yi Henry
• Harari Eli

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/711

  having floating bodies · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10B51/30

  characterised by the memory core region · CPC title