Polymeric coating for semiconductor processing chamber components

Patent metadata

Field	Value
Publication number	US-12548737-B2
Application number	US-202218546174-A
Country	US
Kind code	B2
Filing date	Feb 25, 2022
Priority date	Mar 8, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A component in a semiconductor processing chamber is provided. An electrically conductive semiconductor or metal body has a CTE of less than 10.0×10−6/K. An intermediate layer is disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxy alkane (PFA) layer is disposed over the intermediate layer to form the component.

First claim

What is claimed is:

1 . A semiconductor processing chamber, comprising:
a plasma processing chamber; an electrostatic chuck within the plasma processing chamber; and a component forming a ring around the electrostatic chuck, the component comprising:
an electrically conductive semiconductor or metal body,
wherein the body has a CTE of less than 10.0×10 −6 /K;
an intermediate layer disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer; and
a perfluoroalkoxy alkane (PFA) layer disposed over the intermediate layer to form the component.

2 . The semiconductor processing chamber, as recited in claim 1 , wherein the body is a semiconductor body comprising silicon or silicon carbide.

3 . The semiconductor processing chamber, as recited in claim 2 , wherein the semiconductor body comprises elemental silicon.

4 . The semiconductor processing chamber, as recited in claim 1 , wherein the body has a CTE of less than 5.0×10 −6 /K.

5 . The semiconductor processing chamber, as recited in claim 1 , wherein the intermediate layer is polyethersulfone (PES) resin-based to aid in bonding to the at least one surface of the body.

6 . The semiconductor processing chamber, as recited in claim 1 , wherein the intermediate layer is water or solvent borne to allow for application of the intermediate layer to the at least one surface of the body via spray deposition.

7 . The semiconductor processing chamber, as recited in claim 1 , wherein the PFA layer is applied to the intermediate layer via spray deposition for bonding to the intermediate layer.

8 . The semiconductor processing chamber, as recited in claim 1 ,
wherein the component is exposed to corrosive processes in the plasma processing chamber and the PFA layer is resistant to damage or erosion by the corrosive processes.

9 . The semiconductor processing chamber, as recited in claim 1 , wherein the intermediate layer is fluorinated ethylene propylene resin-based to aid in bonding to the at least one surface of the body.

10 . The semiconductor processing chamber, as recited in claim 1 wherein the fluoropolymer is at least one of fluorinated ethylene propylene (FEP) and polyethersulfone (PES).

11 . A method for forming a component for use in a semiconductor processing chamber, the method comprising:
providing an electrically conductive semiconductor or metal body; wherein the body has a CTE of less than 10.0×10 −6 /K; forming an intermediate layer over at least one surface of the body, the intermediate layer comprising fluoropolymer; forming a perfluoroalkoxy alkane (PFA) layer over the intermediate layer to form the component; and installing the component in a semiconductor processing chamber; wherein the component forms a ring around an electrostatic chuck within the semiconductor processing chamber, the electrostatic chuck supporting a wafer for processing.

12 . The method, as recited in claim 11 , wherein the body is a semiconductor body comprising silicon or silicon carbide.

13 . The method, as recited in claim 12 , wherein the semiconductor body comprises elemental silicon.

14 . The method, as recited in claim 11 , wherein the body has a CTE of less than 5.0×10 −6 /K.

15 . The method, as recited in claim 11 , wherein the intermediate layer is resin-based to aid in bonding to the at least one surface of the body.

16 . The method, as recited in claim 15 , wherein the resin comprises polyethersulfone (PES).

17 . The method, as recited in claim 11 , wherein the intermediate layer is water or solvent borne, and wherein forming an intermediate layer comprises applying the intermediate layer to the at least one surface of the body via spray deposition.

18 . The method, as recited in claim 11 , wherein the PFA layer is applied to the intermediate layer via spray deposition for bonding to the intermediate layer.

19 . The method, as recited in claim 11 :
wherein the semiconductor processing chamber comprises a plasma processing chamber; and wherein the component is exposed to corrosive processes in the plasma processing chamber and the PFA layer is resistant to damage or erosion by the corrosive processes.

20 . The method, as recited in claim 11 , wherein the intermediate layer comprises at least one of fluorinated ethylene propylene and polyethersulfone.

21 . An edge ring for use in a plasma processing chamber, comprising:
an elemental silicon edge ring body; a fluoropolymer coating on at least one surface of the elemental silicon edge ring body; and a perfluoroalkoxy alkane (PFA) coating on the fluoropolymer coating.

Assignees

• Lam Res Corp

Inventors

• Song Yuanping
• Pham Johnny
• Song Yiwei
• Xu Lin
• Kimball Christopher

Classifications

• H10P72/7611

  characterised by edge profile or support profile · CPC title

• H10P72/72

  using electrostatic chucks · CPC title

• H10P72/0421

  for drying etching · CPC title

• H10P72/7616 Primary

  characterised by a coating, a hardness or a material · CPC title

• H01J2237/0213

  Avoiding deleterious effects due to interactions between particles and tube elements · CPC title