Adaptive peripheral component interconnect express link substate initiation for optimal performance and power savings
US-11029748-B2 · Jun 8, 2021 · US
US12547229B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12547229-B2 |
| Application number | US-202418743854-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 14, 2024 |
| Priority date | Jun 14, 2024 |
| Publication date | Feb 10, 2026 |
| Grant date | Feb 10, 2026 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.
Opening claim text (preview).
What is claimed is: 1 . A processor-implemented method for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system, the method comprising: training a neural network; recording, in real time, lane input data of one or more PCIe lanes comprising a PCIe link; generating one or more eye diagrams representing the one or more PCIe lanes based on the lane input data; predicting, by the trained neural network, one or more predicted eye heights for the one or more PCIe lanes; and adjusting a current output swing voltage of one or more PCIe lanes based on the one or more predicted eye heights. 2 . The method of claim 1 , further comprising: dynamically recording a plurality of link input data associated with the PCIe link. 3 . The method of claim 2 , further comprising: creating one or more margins based on the link input data and the lane input data. 4 . The method of claim 3 , wherein the predicting is based on the one or more created margins. 5 . The method of claim 1 , wherein the adjusting comprises: responsive to determining that one of the one or more predicted eye heights is greater than a current output swing voltage of a PCIe lane, raising a current output swing voltage of the PCIe lane. 6 . The method of claim 1 , wherein the adjusting comprises: responsive to determining that one of the one or more predicted eye heights is lower than a current output swing voltage of a PCIe lane, lowering a current output swing voltage of the PCIe lane. 7 . The method of claim 1 , wherein the adjusting is based on an expected link speed and an expected utilization. 8 . A computer system for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system, the computer system comprising: one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage medium, and program instructions stored on at least one of the one or more tangible storage medium for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising: training a neural network; recording, in real time, lane input data of one or more PCIe lanes comprising a PCIe link; generating one or more eye diagrams representing the one or more PCIe lanes based on the lane input data; predicting, by the trained neural network, one or more predicted eye heights for the one or more PCIe lanes; and adjusting a current output swing voltage of one or more PCIe lanes based on the one or more predicted eye heights. 9 . The computer system of claim 8 , further comprising: dynamically recording a plurality of link input data associated with the PCIe link. 10 . The computer system of claim 8 , further comprising: creating one or more margins based on the link input data and the lane input data. 11 . The computer system of claim 8 , wherein the predicting is based on the one or more created margins. 12 . The computer system of claim 8 , wherein the adjusting comprises: responsive to determining that one of the one or more predicted eye heights is greater than a current output swing voltage of a PCIe lane, raising a current output swing voltage of the PCIe lane. 13 . The computer system of claim 8 , wherein the adjusting comprises: responsive to determining that one of the one or more predicted eye heights is lower than a current output swing voltage of a PCIe lane, lowering a current output swing voltage of the PCIe lane. 14 . The computer system of claim 8 , wherein the adjusting is based on an expected link speed and an expected utilization. 15 . A computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system, the computer program product comprising: one or more computer-readable tangible storage medium and program instructions stored on at least one of the one or more tangible storage medium, the program instructions executable by a processor to cause the processor to perform a method comprising: training a neural network; recording, in real time, lane input data of one or more PCIe lanes comprising a PCIe link; generating one or more eye diagrams representing the one or more PCIe lanes based on the lane input data; predicting, by the trained neural network, one or more predicted eye heights for the one or more PCIe lanes; and adjusting a current output swing voltage of one or more PCIe lanes based on the one or more predicted eye heights. 16 . The computer program product of claim 15 , further comprising: dynamically recording a plurality of link input data associated with the PCIe link. 17 . The computer program product of claim 15 , further comprising: creating one or more margins based on the link input data and the lane input data. 18 . The computer program product of claim 15 , wherein the predicting is based on the one or more created margins. 19 . The computer program product of claim 15 , wherein the adjusting comprises: responsive to determining that one of the one or more predicted eye heights is greater than a current output swing voltage of a PCIe lane, raising a current output swing voltage of the PCIe lane. 20 . The computer program product of claim 15 , wherein the adjusting comprises: responsive to determining that one of the one or more predicted eye heights is lower than a current output swing voltage of a PCIe lane, lowering a current output swing voltage of the PCIe lane.
Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title
on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title
Learning methods · CPC title
PCI express · CPC title
Power supply means, e.g. regulation thereof (for memories G11C) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.