Adaptive peripheral component interconnect express link substate initiation for optimal performance and power savings

Patent metadata

Field	Value
Publication number	US-11029748-B2
Application number	US-201615070381-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	Mar 15, 2016
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.

First claim

The invention claimed is:

1. A method performed by a controller of a Peripheral Component Interconnect Express (PCIe) interface, comprising:
determining that a first burst of data is being transmitted on a PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol;
configuring a timer to signal when an entry latency period has elapsed after determining that the PCIe link has entered an idle state after completing transmission of a first packet in the plurality of packets;
causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, wherein the PCIe link becomes active when a second packet in the plurality of packets is available for transmission;
increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data; and
updating the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst.

2. The method of claim 1 , wherein increasing the entry latency period comprises:
doubling the entry latency period.

3. The method of claim 1 , further comprising:
decreasing the entry latency period when the PCIe interface does not enter the low-power state between transmissions of a pair of packets in the plurality of packets.

4. The method of claim 1 , further comprising:
decreasing the entry latency period when the number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data is less than a second threshold that defines a minimum number of entries into the low-power state per burst of data; and
updating the second threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated second threshold to be used in the subsequent second burst.

5. The method of claim 4 , wherein decreasing the entry latency period comprises:
halving the entry latency period.

6. The method of claim 4 , wherein decreasing the entry latency period comprises:
restoring a previous time period used for the entry latency period.

7. The method of claim 1 , wherein causing one or more circuits of the PCIe interface to enter the low-power state comprises:
disabling one or more circuits of a transceiver coupled to the PCIe interface.

8. The method of claim 1 , wherein causing one or more circuits of the PCIe interface to enter the low-power state comprises:
disabling or gating a clock signal used by one or more circuits of the PCIe interface.

9. The method of claim 1 , wherein causing one or more circuits of the PCIe interface to enter the low-power state comprises:
causing circuits in two or more devices coupled to the PCIe interface to enter the low-power state.

10. An apparatus comprising:
a Peripheral Component Interconnect Express (PCIe) interface adapted to couple the apparatus to a PCIe link; and
a controller configured to determine that a first burst of data is being transmitted on the PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol, and wherein during transmission of the first burst of data the controller is further configured to:
determine when the PCIe link has entered an idle state;
enable a timer adapted to signal when an entry latency period has elapsed after determining that the PCIe link has entered the idle state after completing transmission of a first packet in the plurality of packets;
cause one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, wherein the PCIe link becomes active when a second packet in the plurality of packets is available for transmission;
increase the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data; and
update the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst.

11. The apparatus of claim 10 , wherein the controller is configured to:
increase the entry latency period comprises double the entry latency period.

12. The apparatus of claim 10 , wherein the controller is configured to:
decrease the entry latency period when the PCIe interface does not enter the low-power state between transmissions of a pair of packets in the plurality of packets.

13. The apparatus of claim 10 , wherein the controller is configured to:
decrease the entry latency period when the number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data is less than a second threshold that defines a minimum number of entries into the low-power state per burst of data; and
update the second threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated second threshold to be used in the subsequent second burst.

14. The apparatus of claim 13 , wherein the controller is configured to:
decrease the entry latency period by halving the entry latency period.

15. The apparatus of claim 13 , wherein the controller is configured to:
decrease the entry latency period by restoring a previous time period used for the entry latency period.

16. The apparatus of claim 10 , wherein the controller is configured to:
cause the one or more circuits of the PCIe interface to enter the low-power state by disabling one or more circuits of a transceiver coupled to the PCIe interface.

17. The apparatus of claim 10 , wherein the controller is configured to:
cause the one or more circuits of the PCIe interface to enter the low-power state by disabling or gating a clock signal used by one or more circuits of the PCIe interface.

18. The apparatus of claim 10 , wherein the controller is configured to:
cause the one or more circuits of the PCIe interface to enter the low-power state by causing circuits in two or more devices coupled to the PCIe interface to enter the low-power state.

19. An apparatus comprising:
means for determining activity on a PCIe link, including determining when a first burst of data is being transmitted on the PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol;
means for managing power consumption in a Peripheral Component Interconnect Express (PCIe) interface, and configured to transition the PCIe interface between at least a first state and a second state;
means for configuring a timer, wherein the means fo

Assignees

• Qualcomm Inc

Inventors

• Klacar Neven
• Krishnamoorthy Muralidhar
• Sukumar Hariharan

Classifications

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• Y02D30/50

  in wire-line communication networks, e.g. low power modes or reduced link rate · CPC title