Peripheral component interconnect express (PCIe) device enumeration via a PCIe switch

Patent metadata

Field	Value
Publication number	US-10824581-B2
Application number	US-201715634396-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Jun 27, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

Described herein are enhancements for managing multi-host Peripheral Component Interconnect Express (PCIe) switching. In one implementation, a PCIe switch coupled to a host processing system and PCIe slots may receive enumeration requests from the host processing system to identify available PCIe devices. In response to the enumeration requests, the PCIe switch may transfer responses to the host processing system indicating device identifier information for PCIe devices associated with the PCIe slots even if one or more of the PCIe devices is not currently installed.

First claim

What is claimed is:

1. A Peripheral Component Interconnect Express (PCIe) switch configured to be communicatively coupled to a host processing system and to a plurality of PCIe slots, the PCIe switch comprising:
one or more non-transitory computer-readable storage media;
a processing system operatively coupled with the one or more computer-readable storage media; and
program instructions stored on the one or more computer-readable storage media that, when read and executed by the processing system, direct the processing system to at least:
receive at least one PCIe enumeration request from the host processing system to identify available PCIe devices,
in response to the at least one PCIe enumeration request, transfer one or more responses to the host processing system indicating device identifier information for a plurality of PCIe devices corresponding to the plurality of PCIe slots, wherein:
at least one PCIe device of the plurality of PCIe devices is not installed in an unoccupied PCIe slot of the plurality of PCIe slots, and
the device identifier information includes device identifier information for the at least one PCIe device expected to be installed in the unoccupied PCIe slot, to enable the host processing system to allocate addressing resources for the at least one PCIe device that is not yet installed in the unoccupied PCIe slot.

2. The PCIe switch of claim 1 , wherein the device identifier information comprises a vendor identifier and a device identifier for the at least one PCIe device.

3. The PCIe switch of claim 1 , wherein the one or more responses further indicate whether the at least one PCIe device is currently installed in any PCIe slot of the plurality of PCIe slots.

4. The PCIe switch of claim 1 , wherein the program instructions further direct the processing system to:
receive a write command from the host processing system directed at a target PCIe device of the plurality of PCIe devices, wherein the write command provides configuration data for the target PCIe device;
cache the write command;
identify whether the target PCIe device is installed in a PCIe slot of the plurality of PCIe slots; and
responsive to the target PCIe device being installed in a PCIe slot, forward the write command to the target PCIe device.

5. The PCIe switch of claim 4 , wherein the program instructions further direct the processing system to:
responsive to the target PCIe device not being installed in a PCIe slot, identify an installation of the target PCIe device in an available PCIe slot of the plurality of PCIe slots; and
in response to the installation, forward the write command to the installed target PCIe device.

6. The PCIe switch of claim 4 , wherein the write command comprises memory address allocation for the host processing system.

7. The PCIe switch of claim 1 , wherein the plurality of PCIe devices comprises a data storage device.

8. The PCIe switch of claim 1 , wherein the plurality of PCIe devices comprises a graphics processing unit.

9. A computing system comprising:
a plurality of Peripheral Component Interconnect Express (PCIe) slots; and
a PCIe switch communicatively coupled to the plurality of PCIe slots via PCIe lanes, the PCIe switch configured to:
receive at least one PCIe enumeration request from a host processing system to identify available PCIe devices;
in response to the at least one PCIe enumeration request, transfer one or more responses to the host processing system indicating device identifier information for a plurality of PCIe devices corresponding to the plurality of PCIe slots, wherein:
at least one PCIe device of the plurality of PCIe devices is not installed in an unoccupied PCIe slot of the plurality of PCIe slots, and
the device identifier information includes device identifier information for the at least one PCIe device expected to be installed in the unoccupied PCIe slot, to enable the host processing system to allocate addressing resources for the at least one PCIe device that is not yet installed in the unoccupied PCIe slot; and

in response to the at least one PCIe device being installed in the previously unoccupied PCIe slot, providing an indication to the host processing system that the at least one PCIe device has been made available.

10. The computing system of claim 9 , wherein the device identifier information comprises a vendor identifier and a device identifier for the at least one PCIe device.

11. The computing system of claim 9 , wherein the one or more responses further indicate whether the at least one PCIe device is currently installed in any PCIe slot of the plurality of PCIe slots.

12. The computing system of claim 9 , wherein the PCIe switch is further configured to:
receive a write command from the host processing system directed at a target PCIe device of the plurality of PCIe devices, wherein the write command provides configuration data for the target PCIe device;
cache the write command;
identify whether the target PCIe device is installed in a PCIe slot of the plurality of PCIe slots; and
responsive to the target PCIe device being installed in a PCIe slot, forward the write command to the target PCIe device.

13. The computing system of claim 12 , wherein the PCIe switch is further configured to:
responsive to the target PCIe device not being installed in a PCIe slot, identify an installation of the target PCIe device in an available PCIe slot of the plurality of PCIe slots; and
in response to the installation, forward the write command to the installed target PCIe device.

14. The computing system of claim 12 , wherein the write command comprises memory address allocation for the host processing system.

15. The computing system of claim 9 , wherein the plurality of PCIe devices comprises a data storage device.

16. The computing system of claim 9 , wherein the plurality of PCIe devices comprises a graphics processing unit.

17. A computing system comprising:
a host processing system;
a plurality of Peripheral Component Interconnect Express (PCIe) slots; and
a PCIe switch communicatively coupled to the plurality of PCIe slots and to the host processing system via PCIe lanes, the PCIe switch configured to:
receive at least one PCIe enumeration request from the host processing system to identify available PCIe devices; and
in response to the at least one PCIe enumeration request, transfer one or more responses to the host processing system indicating device identifier information for a plurality of PCIe devices corresponding to the plurality of PCIe slots, wherein:
at least one PCIe device of the plurality of PCIe devices is not installed in an unoccupied PCIe slot of the plurality of PCIe slots, and
the device identifier information includes device identifier information for the at least one PCIe device expected to be installed in the unoccupied PCIe slot, to enable the host processing system to allocate addressing resources for the at least one PCIe device that is not yet installed in the unoccupied PCIe slot; and

the host processing system is configured to allocate addressing resources for the at least one PCIe device that is not yet installed in the unoccupied PCIe slot.

18. The computing system of claim 17 , wherein the plurality of PCIe devices comprises a data storage device.

19. The computing system of claim 17 , wherein the plurality of PCIe devices comprises a graphics processing unit.

20. The computing system of claim 17 , wherein the PCIe switch is further configured to:
receive a write comman

Assignees

• Western Digital Tech Inc

Inventors

• Nash Berck
• Hess Randall
• Walker Michael
• Reiser James Michael

Classifications

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• G06F2213/0026

  PCI express · CPC title