Display with gate driver circuitry controlled by true and complementary clock signals

Patent metadata

Field	Value
Publication number	US-12547207-B2
Application number	US-202418931492-A
Country	US
Kind code	B2
Filing date	Oct 30, 2024
Priority date	Jan 11, 2024
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A display may include an array of pixels that receive row control signals from gate driver circuitry. The gate driver circuitry can include a chain of gate drivers configured to receive one or more clock signals. The gate driver circuitry can further include inverters configured to invert the one or more clock signals to generate inverted clock signals. The clock signals and the inverted clock signals can be conveyed to the chain of gate drivers. Falling edges of the clock signals and the inverted clock signals can be used to trigger assertions and deassertions of the row control signals. Operated in this way, the power consumption of the gate driver circuitry can be reduced.

First claim

What is claimed is:

1 . A display comprising:
an array of pixels; a first gate driver circuit configured to generate a first gate output signal that is conveyed to one or more rows of pixels in the array; a second gate driver circuit configured to generate a second gate output signal that is conveyed to one or more rows of pixels in the array; a first clock signal line through which a first clock signal is conveyed to the first gate driver circuit; a first inverter configured to receive the first clock signal from the first clock signal line; and a reset line on which a reset signal is provided, wherein the reset line is coupled to one or more reset transistors in the first gate driver circuit and is coupled to one or more reset transistors in the second gate driver circuit.

2 . The display of claim 1 , further comprising:
a second clock signal line on which a second clock signal is provided; and a second inverter configured to receive the second clock signal from the second clock signal line.

3 . The display of claim 2 , wherein:
the second gate driver circuit has an input coupled to the first gate driver circuit; and the second gate driver circuit is configured to receive an inverted version of the first clock signal from the first inverter.

4 . The display of claim 3 , further comprising:
a third gate driver circuit configured to generate a third gate output signal and having an input coupled to the second gate driver circuit, wherein the third gate driver circuit is configured to receive the second clock signal; and a fourth gate driver circuit configured to generate a fourth gate output signal and having an input coupled to the third gate driver circuit, wherein the fourth gate driver is configured to receive an inverted version of the second clock signal from the second inverter.

5 . The display of claim 4 , wherein:
the first gate output signal is conveyed to first and second rows of pixels in the array; the second gate output signal is conveyed to third and fourth rows of pixels in the array; the third gate output signal is conveyed to fifth and sixth rows of pixels in the array; and the fourth gate output signal is conveyed to seventh and eighth rows of pixels in the array.

6 . The display of claim 4 , wherein:
the first gate output signal is conveyed to a first group of four rows of pixels in the array; the second gate output signal is conveyed to a second group of four rows of pixels in the array; the third gate output signal is conveyed to a third group of four rows of pixels in the array; and the fourth gate output signal is conveyed to a fourth group of four rows of pixels in the array.

7 . The display of claim 2 , wherein:
the second gate driver circuit has an input coupled to the first gate driver circuit; and the second gate driver circuit is configured to receive the second clock signal.

8 . The display of claim 7 , further comprising:
a third gate driver circuit configured to generate a third gate output signal and having an input coupled to the second gate driver circuit, wherein the third gate driver circuit is configured to receive an inverted version of the first clock signal from the first inverter; and a fourth gate driver circuit configured to generate a fourth gate output signal and having an input coupled to the third gate driver circuit, wherein the fourth gate driver is configured to receive an inverted version of the second clock signal from the second inverter.

9 . The display of claim 8 , wherein:
the first gate output signal is conveyed to first and second rows of pixels in the array; the second gate output signal is conveyed to third and fourth rows of pixels in the array; the third gate output signal is conveyed to fifth and sixth rows of pixels in the array; and the fourth gate output signal is conveyed to seventh and eighth rows of pixels in the array.

10 . The display of claim 7 , further comprising:
a third gate driver circuit configured to generate a third gate output signal and having an input coupled to the second gate driver circuit; a fourth gate driver circuit configured to generate a fourth gate output signal and having an input coupled to the third gate driver circuit; and a first multiplexer having a first input configured to receive an inverted version of the first clock signal from the first inverter, a second input configured to receive the first clock signal, and an output coupled to the third gate driver circuit.

11 . The display of claim 10 , further comprising:
a second multiplexer having a first input configured to receive an inverted version of the second clock signal from the second inverter, a second input configured to receive the second clock signal, and an output coupled to the fourth gate driver circuit.

12 . The display of claim 3 , wherein:
the one or more rows of pixels configured to receive the first gate output signal are further configured to receive pixel values adjusted based on a first set of luminance compensation coefficients; and the one or more rows of pixels configured to receive the second gate output signal are further configured to receive pixel values adjusted based on a second set of luminance compensation coefficients different than the first set of luminance compensation coefficients.

13 . A method of operating a display, comprising:
with an array of pixels, displaying image content; with a first gate driver, outputting a first gate output signal to one or more rows of pixels in the array; with a second gate driver, outputting a second gate output signal to one or more rows of pixels in the array; with the first gate driver, receiving a first clock signal; with a first inverter, receiving the first clock signal and outputting an inverted version of the first clock signal; with a falling clock edge of the first clock signal, triggering assertion of the first gate output signal; and with a falling clock edge of the inverted version of the first clock signal, triggering assertion of the second gate output signal.

14 . The method of claim 13 , further comprising:
with the second gate driver, receiving the inverted version of the first clock signal from the first inverter.

15 . The method of claim 13 , further comprising:
with a third gate driver, outputting a third gate output signal to one or more rows of pixels in the array; with a fourth gate driver, outputting a fourth gate output signal to one or more rows of pixels in the array; with the third gate driver, receiving a second clock signal; and with a second inverter, receiving the second clock signal and outputting an inverted version of the second clock signal to the fourth gate driver.

16 . The method of claim 13 , further comprising:
with a third gate driver, outputting a third gate output signal to one or more rows of pixels in the array; with a fourth gate driver, outputting a fourth gate output signal to one or more rows of pixels in the array; and with a multiplexer, receiving the inverted version of the first clock signal, receiving the first clock signal, and outputting either the inverted version of the first clock signal or the first clock signal to the third gate driver.

17 . The method of claim 13 , further comprising:
providing a reset signal to one or more reset transistors in the first gate driver; and providing the reset signal one or more reset transistors in the second gate driver.

18 . A display comprising:
an array of pixels; and gate driver circuitry configured to receive onl

Assignees

• Apple Inc

Inventors

• Choo Gihoon
• Tsai Tsung-Ting
• Yang Shyuan
• Jamshidi Roudbari Abbas
• Lin Chin-Wei
• Cheng Mao-Hsun
• KABIR Salman
• Chang Ting-Kuo
• Rieutort-Louis Warren S
• Che Yuchi
• Li Qing
• Hsieh Cheng-Chih

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title