Adding sealing material to wafer edge for wafer bonding

Patent metadata

Field	Value
Publication number	US-12543604-B2
Application number	US-202318151663-A
Country	US
Kind code	B2
Filing date	Jan 9, 2023
Priority date	Sep 19, 2022
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

First claim

What is claimed is:

1 . A method comprising:
forming a first sealing layer at a first edge region of a first wafer; bonding the first wafer to a second wafer to form a wafer stack, wherein at a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, and wherein the first edge region and the second edge region comprise bevels; performing an edge trimming process on the wafer stack, wherein after the edge trimming process, the second edge region of the second wafer is at least partially removed, and wherein a portion of the first sealing layer is left as a part of the wafer stack; and forming an interconnect structure as a part of the second wafer, wherein the interconnect structure comprises redistribution lines electrically connected to integrated circuit devices in the second wafer.

2 . The method of claim 1 , wherein the first sealing layer is formed through spin- on coating.

3 . The method of claim 1 , wherein the first sealing layer is formed after the first wafer is bonded to the second wafer.

4 . The method of claim 1 , wherein the first sealing layer is formed before the first wafer is bonded to the second wafer, and wherein the forming the first sealing layer comprises:
forming the first sealing layer on the first wafer; and performing a planarization process to level a first top surface of the first sealing layer with a second top surface of the first wafer.

5 . The method of claim 4 , wherein the forming the first sealing layer further comprises performing an etching process to shape edges of the first sealing layer.

6 . The method of claim 4 further comprising, after the planarization process, forming a bond layer on the first wafer and the first sealing layer.

7 . The method of claim 4 further comprising, before the first wafer is bonded to the second wafer:
forming a second sealing layer on the second wafer; and
performing an additional planarization process on the second sealing layer and the second wafer.

8 . The method of claim 4 further comprising:
removing a metallic feature in the first wafer to form a recess, wherein the first sealing layer comprises a portion filling the recess, and wherein after the planarization process, the portion of the first sealing layer remains in the recess.

9 . The method of claim 1 , wherein the edge trimming process results in a recess to be formed in the wafer stack, and wherein a bottom of the recess is higher than a bonding interface between the first wafer and the second wafer.

10 . The method of claim 1 , wherein the edge trimming process results in a recess being formed in the wafer stack, and wherein both of the first wafer and the second wafer are trimmed.

11 . A method comprising:
forming a first wafer comprising:
a first substrate;
at least one first dielectric layer over the first substrate;
a first sealing layer at a first edge region of the first wafer, wherein a first top surface of the at least one first dielectric layer is coplanar with a second top surface of the first sealing layer; and
a first bond layer overlapping both of the at least one first dielectric layer and the first sealing layer;
forming a second wafer, wherein the second wafer comprises:
a second substrate;
at least one second dielectric layer underlying the second substrate;
a second sealing layer at a second edge region of the second wafer, wherein bottom surfaces of the at least one second dielectric layer and the second sealing layer are coplanar with each other; and
a second bond layer overlapped by both of the at least one second dielectric layer and the second sealing layer; and
bonding the second wafer to the first wafer by bonding the second bond layer to the first bond layer.

12 . The method of claim 11 , wherein the first bond layer comprises an inorganic dielectric material.

13 . The method of claim 11 , wherein the first bond layer comprises a straight edge perpendicular to a bonding interface between the first bond layer and the second bond layer.

14 . The method of claim 11 , wherein the first sealing layer and the second sealing layer are separated from each other by the first bond layer and the second bond layer.

15 . The method of claim 11 , wherein the first sealing layer and the second sealing layer comprise different materials.

16 . The method of claim 11 , wherein the first sealing layer and the second sealing layer are capable of enduring a temperature higher than about 200° C. without being damaged.

17 . The method of claim 11 , wherein the first wafer further comprises a dummy feature underlying and contacting the first bond layer, wherein the dummy feature and the first sealing layer are formed of a same material.

18 . A method comprising:
forming a first wafer comprising:
a first semiconductor substrate, wherein the first semiconductor substrate comprises a first curved surface in a first edge region of the first wafer;
at least one first dielectric layer over the first semiconductor substrate;
a first sealing layer, wherein the first sealing layer comprises a second curved surface, and wherein the second curved surface is in physical contact with one of the first semiconductor substrate and the at least one first dielectric layer; and
a first bond layer comprising a planar bottom surface contacting both of the at least one first dielectric layer and the first sealing layer;
forming a second wafer comprising:
a second semiconductor substrate; and
a second bond layer; and
bonding the second wafer to the first wafer, with the second bond layer bonding to the first bond layer.

19 . The method of claim 18 , wherein the second semiconductor substrate comprises a third curved surface in a second edge region of the second wafer, and the second wafer comprises:
at least one second dielectric layer under the second semiconductor substrate; and a second sealing layer under the at least one second dielectric layer and over the second bond layer, wherein the second sealing layer comprises a fourth curved surface in the second edge region of the second wafer, with the fourth curved surface contacting the third curved surface.

20 . The method of claim 19 , wherein the first sealing layer is separated from the second sealing layer by the first bond layer and the second bond layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Yi
• Lin Yu-Hung
• Wang Wei-Ming
• Chen Chen
• Tai Shih-Peng
• Yee Kuo-Chung

Classifications

• H01L2924/3512

  Electricity · mapped topic

• H01L2225/06541

  Electricity · mapped topic

• H01L2225/06527

  Electricity · mapped topic

• H01L2225/06524

  Electricity · mapped topic

• H01L2225/0651

  Electricity · mapped topic