Packages with Si-substrate-free interposer and method forming same

Patent metadata

Field	Value
Publication number	US-11610858-B2
Application number	US-202017106744-A
Country	US
Kind code	B2
Filing date	Nov 30, 2020
Priority date	Apr 7, 2017
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

First claim

What is claimed is:

1. A package comprising:
a redistribution structure comprising:
a first plurality of dielectric layers;
a plurality of redistribution lines extending into the first plurality of dielectric layers, wherein top surfaces of the plurality of redistribution lines are higher than top surfaces of respective ones of the first plurality of dielectric layers;
a second plurality of dielectric layers over the first plurality of dielectric layers; and
a plurality of metal lines and plurality of metal vias, wherein each of the plurality of metal lines and a corresponding underlying one of the plurality of metal vias are in a same dielectric layer in the second plurality of dielectric layers, wherein top surfaces of the plurality of metal lines are coplanar with top surfaces of the respective ones of the second plurality of dielectric layers; and

a first device die over and bonded to the redistribution structure.

2. The package of claim 1 , wherein the first plurality of dielectric layers comprise polymers, and the second plurality of dielectric layers comprise low-k dielectric materials.

3. The package of claim 1 , wherein the plurality of metal lines and the plurality of vias form dual damascene structures, and portions of the plurality of redistribution lines comprises trace portions and via portions underlying the trace portions, and the via portions have upper portions wider than respective lower portions.

4. The package of claim 1 , further comprising a through-via penetrating through the second plurality of dielectric layers, wherein the through-via electrically connects the plurality of redistribution lines to the first device die.

5. The package of claim 4 , wherein the through-via comprises a substantially straight edge extending from a top surface of a top dielectric layer of the second plurality of dielectric layers to a bottom surface of a bottom dielectric layer of the second plurality of dielectric layers.

6. The package of claim 1 , further comprising:
a second device die over and bonded to the redistribution structure, wherein the first device die and the second device die are electrically interconnected through some of the plurality of metal lines and the plurality of metal vias.

7. The package of claim 1 , further comprising:
a bond pad physically contacting a semiconductor substrate of the first device die, wherein the bond pad is signally disconnected from all devices in the first device die.

8. The package of claim 7 , wherein the bond pad further extends into the semiconductor substrate of the first device die.

9. The package of claim 1 , further comprising a silicon substrate over and attached to the first device die, wherein the silicon substrate is free from active devices and passive devices thereon.

10. A package comprising:
a plurality of dielectric layers;
a plurality of metal lines and vias in the plurality of dielectric layers, wherein the plurality of metal lines and vias form damascene structures;
a first dielectric layer underlying the plurality of dielectric layers; and
a redistribution line comprising a trace portion and a via portion, wherein the trace portion has a bottom surface level with a bottom surface of the first dielectric layer, and a first top surface at an intermediate level between the bottom surface and a second top surface of the first dielectric layer;
a solder region underlying the redistribution line;
a device die over the plurality of dielectric layers, wherein the device die is electrically connected to the solder region through the plurality of metal lines and vias and the redistribution line; and
a dielectric gap-filling region comprising portions contacting opposing sidewalls of the device die to form vertical interfaces.

11. The package of claim 10 , wherein the via portion of the redistribution line is tapered, with upper portions of the via portion being wider than respective lower portions of the via portion.

12. The package of claim 10 , wherein no semiconductor substrate is located between the solder region and the device die.

13. The package of claim 10 , further comprising:
an additional redistribution line over and contacting the redistribution line;
a second dielectric layer, wherein top surfaces of the second dielectric layer and the additional redistribution line are coplanar; and
a through-via over and physically contacting the additional redistribution line, wherein the through-via penetrates through the plurality of dielectric layers.

14. The package of claim 10 , wherein the first dielectric layer comprises a polymer, and the plurality of dielectric layers comprise low-k dielectric materials.

15. The package of claim 10 , further comprising a silicon substrate over and attached to the device die, wherein the silicon substrate is free from active devices and passive devices thereon.

16. The package of claim 15 , further comprising a metal feature physically contacting both of the silicon substrate and a semiconductor substrate of the device die.

17. The package of claim 16 , further comprising a dielectric region comprising:
a first portion comprising a first sidewall contacting a second sidewall of the device die to form a vertical interface; and
a second portion overlapping the device die, wherein the metal feature extends into both of the second portion of the dielectric region and the semiconductor substrate of the device die.

18. A package comprising:
a plurality of dielectric layers;
a plurality of dual damascene structures in the plurality of dielectric layers, wherein each of the damascene structures comprises a via and a metal line over and joined to the via;
a plurality of through-dielectric vias penetrating through the plurality of dielectric layers, wherein a substantially straight edge of each of the plurality of through-dielectric vias is in contact with edges of the plurality of dielectric layers;
an insulation layer over the plurality of dielectric layers;
a plurality of bond pads in the insulation layer and electrically coupling to the plurality of through-dielectric vias and the plurality of dual damascene structures;
a device die over and bonded to the insulation layer and portions of the plurality of bond pads;
a polymer layer underlying the plurality of dielectric layers;
a redistribution line extending into the polymer layer; and
a solder region underlying and electrically connected to one of the plurality of dual damascene structures through the redistribution line, wherein the package is free from semiconductor substrate between the solder region and the device die.

19. The package of claim 18 , wherein the redistribution line comprises a trace portion overlying and contacting the polymer layer, and a via portion extending into the polymer layer.

20. The package of claim 18 , wherein the redistribution line comprises a trace portion underlying and contacting the polymer layer, and a via portion extending into the polymer layer.

21. The package of claim 20 , wherein the via portion of the redistribution line is tapered, with upper portions of the via portion being wider than respective lower portions of the via portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ming-Fa
• Yu Chen-Hua

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/0198

  batch processes · CPC title