Three-dimensional memory devices and fabricating methods thereof

Patent metadata

Field	Value
Publication number	US-12543310-B2
Application number	US-202217704740-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Aug 30, 2021
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive/dielectric stack on a substrate, a plurality of channel structures in the alternating conductive/dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive/dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive/dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive/dielectric stack.

First claim

What is claimed is:

1 . A three-dimensional ( 3 D) memory device, comprising:
an alternating conductive/dielectric stack on a substrate, wherein the alternating conductive/dielectric stack includes a first portion and a second portion relative to the substrate, and wherein the first portion is further from the substrate than the second portion; a plurality of channel structures in the alternating conductive/dielectric stack; and a plurality of gate line slit (GLS) structures in the alternating conductive/dielectric stack, each including:
a plurality of first type GLS portions penetrating the first portion and the second portion of the alternating conductive/dielectric stack; and
a plurality of second type GLS portions penetrating only the first portion of the alternating conductive/dielectric stack, wherein a conductive wall in a second type GLS portion of the plurality of second type GLS portions is in contact with a conductive wall in a first type GLS portion of the plurality of first type GLS portions along a word line direction.

2 . The 3D memory device of claim 1 , wherein the plurality of first type GLS portions and the plurality of second type GLS portions are arranged in staggered positions next to each other in a bit line direction.

3 . The 3D memory device of claim 1 , further including a memory block including at least three memory fingers, wherein two GLS structures are located on edges of the memory block.

4 . The 3D memory device of claim 3 , wherein each second type GLS portion of one of the two GLS structures is aligned with another second type GLS portion of another of the two GLS structures in a bit line direction.

5 . The 3D memory device of claim 3 , wherein each second type GLS portion of one of the two GLS structures overlaps with the first type GLS portion of another of the two GLS structures in a bit line direction.

6 . The 3D memory device of claim 1 , further including a memory block including at least three memory fingers wherein a middle memory finger is sandwiched by two GLS structures.

7 . The 3D memory device of claim 6 , wherein each second type GLS portion of one of the two GLS structures is aligned with another second type GLS portion of another of the two GLS structures in a bit line direction.

8 . The 3D memory device of claim 6 , wherein each second type GLS portion of one of the two GLS structures overlaps with the first type GLS portion of another of the two GLS structures in a bit line direction.

9 . The 3D memory device of claim 1 , further including a memory block including at least three memory fingers, wherein each memory finger is sandwiched by two GLS structures.

10 . The 3D memory device of claim 9 , wherein each second type GLS portion of one GLS structure overlaps with the first type GLS portion in an adjacent second type GLS structure in a bit line direction, and is aligned with another second type GLS portion in a next GLS structure in the bit line direction.

11 . The 3D memory device of claim 9 , wherein each second type GLS portion of one GLS structure located on an edge of the memory block overlaps with the first type GLS portion in an adjacent second type GLS structure in a bit line direction, and is aligned with another second type GLS portion in another GLS structure located on another edge of the memory block in the bit line direction.

12 . The 3D memory device of claim 1 , wherein a length of the second type GLS portion along the word line direction is equal to or less than a half width of a memory finger in a bit line direction.

13 . The 3D memory device of claim 1 , wherein each channel structure includes:
a functional layer on a sidewall of a channel hole; a dielectric filling structure in the channel hole; and a channel layer between the functional layer and the dielectric filling structure.

14 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a first alternating dielectric stack on a substrate; forming a second alternating dielectric stack on the first alternating dielectric stack, wherein the first alternating dielectric stack is closer to the substrate than the second alternating dielectric stack; forming a plurality of sacrificial structures in the second alternating dielectric stack; forming a plurality of gate line slits (GLSs), each including:
a plurality of first type GLS segments penetrating the second alternating dielectric stack and the first alternating dielectric stack; and
a plurality of second type GLS segments penetrating only the second alternating dielectric stack, wherein a conductive wall in a second type GLS portion of the plurality of second type GLS segments is in contact with a conductive wall in a first type GLS portion of the plurality of first type GLS segments along a word line direction;
transforming the second alternating dielectric stack and the first alternating dielectric stack into an alternating conductive/dielectric stack; and forming a GLS structure in each GLS.

15 . The method of claim 14 , wherein forming the plurality of GLSs includes forming the plurality of first type GLS segments and the plurality of second type GLS segments in staggered positions next to each other in a bit line direction.

16 . The method of claim 14 , wherein forming the GLS structure in each GLS includes:
forming a plurality of first type GLS portions in the plurality of first type GLS segments, each first type GLS portion penetrating the alternating conductive/dielectric stack; and forming a plurality of second type GLS portions in the plurality of second type GLS segments, each second type GLS portion extending only into a first alternating conductive/dielectric stack, wherein the alternating conductive/dielectric stack includes the first alternating conductive/dielectric stack and a second alternating conductive/dielectric stack, and wherein the first alternating conductive/dielectric stack is farther from the substrate than the second alternating conductive/dielectric stack.

17 . The method of claim 14 , wherein forming the second alternating dielectric stack and the plurality of sacrificial structures includes:
forming one or more dielectric layer pairs on the first alternating dielectric stack; forming a plurality of recesses in the one or more dielectric layer pairs; forming a sacrificial structure in each recess; and forming one or more additional dielectric layer pairs to cover the plurality of sacrificial structures.

18 . The method of claim 14 , wherein forming the plurality of GLSs includes forming the plurality of first type GLS segments and the plurality of second type GLS segments in a same etching process, wherein an etching ratio of dielectric pairs is larger than an etching ratio of the sacrificial structures.

19 . The method of claim 14 , further including:
before forming the second alternating dielectric stack, forming a plurality of sacrificial lower channel filling structures in the first alternating dielectric stack; and after forming the second alternating dielectric stack, forming a plurality of channel structures penetrating the second alternating dielectric stack and the first alternating dielectric stack by removing the plurality of sacrificial lower channel filling structures and portions of the second alternating dielectric stack corresponding to the plurality of sacrificial lower channel filling structures.

20 . The method of claim 14 , wherein a length of the second type GLS portion along the word line direction

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title