Electronic structures comprising multiple, adjoining high-k dielectric materials and related electronic devices, systems, and methods

Patent metadata

Field	Value
Publication number	US-12543308-B2
Application number	US-202016862150-A
Country	US
Kind code	B2
Filing date	Apr 29, 2020
Priority date	Apr 29, 2020
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

An electronic structure comprising stacks comprising alternating dielectric materials and conductive materials in a cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks and in a pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material in the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials in the cell region of the electronic structure. The cell high-k dielectric material adjoins a portion of the pillar high-k dielectric material. Additional electronic structures are disclosed, as are related electronic devices, systems, and methods of forming an electronic device.

First claim

What is claimed is:

1 . An electronic structure comprising:
stacks comprising alternating dielectric materials and conductive materials in cell regions of the electronic structure; a pillar high-k dielectric material in pillar regions of the electronic structure, the stacks disposed directly and continuously between neighboring ones of the pillar regions and the pillar high-k dielectric material of each of the neighboring ones of the pillar regions adjacent and coextensive with a different opposing sidewall of a corresponding one of the stacks disposed directly and continuously therebetween; an etch stop material directly adjacent to and between the dielectric materials of the stacks and the pillar high-k dielectric material; a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material adjacent to the pillar high-k dielectric material in the pillar regions of the electronic structure; a cell high-k dielectric material surrounding horizontal surfaces and vertical surfaces of the conductive materials in the cell regions of the electronic structure, and the cell high-k dielectric material extending continuously between and adjoining a portion of the pillar high-k dielectric material of each of the neighboring ones of the pillar regions; and a first effective gate length of the conductive materials in the cell regions proximal to the pillar high-k dielectric material of the neighboring ones of the pillar regions relatively greater than a second effective gate length of the conductive materials in the cell regions distal to the pillar high-k dielectric materials.

2 . The electronic structure of claim 1 , wherein the pillar high-k dielectric material and the cell high-k dielectric material separate the stacks from the channel material.

3 . The electronic structure of claim 1 , wherein a total thickness of the pillar high-k dielectric material and the cell high-k dielectric material is from about 2 nm to about 20 nm.

4 . The electronic structure of claim 1 , wherein the adjoining pillar high-k dielectric material and the cell high-k dielectric material are proximal to the conductive materials of the stacks.

5 . The electronic structure of claim 1 , wherein the pillar high-k dielectric material is proximal to the dielectric materials of the stacks and to the conductive materials of the stacks.

6 . The electronic structure of claim 5 , wherein the cell high-k dielectric material is not proximal to vertical surfaces of the dielectric materials of the stacks.

7 . The electronic structure of claim 1 , wherein a length of the pillar high-k dielectric material is coextensive with a length of the stacks.

8 . The electronic structure of claim 1 , wherein the pillar high-k dielectric material and the cell high-k dielectric material comprise materials of different chemical compositions.

9 . The electronic structure of claim 1 , wherein the pillar high-k dielectric material and the cell high-k dielectric material comprise the same chemical composition.

10 . The electronic structure of claim 1 , wherein surfaces of the cell high-k dielectric material are substantially planar.

11 . The electronic structure of claim 1 , wherein a portion of the cell high-k dielectric material adjoining the pillar high-k dielectric material protrudes above an upper horizontal surface of the conductive materials of the stacks and protrudes below a lower horizontal surface of the conductive materials of the stacks.

12 . The electronic structure of claim 1 , wherein a portion of the cell high-k dielectric material adjoining the pillar high-k dielectric material protrudes above an upper horizontal surface of the cell high-k dielectric material and protrudes below a lower horizontal surface of the cell high-k dielectric material.

13 . The electronic structure of claim 1 , wherein portions of the conductive materials of the stacks proximal to the pillar regions protrude above an upper horizontal surface of the conductive materials of the stacks and protrude below a lower horizontal surface of the conductive materials of the stacks.

14 . The electronic structure of claim 1 , wherein the conductive materials of the stacks distal to the pillar high-k dielectric materials comprise a substantially rectangular cross-sectional shape.

15 . The electronic structure of claim 1 , wherein the conductive materials of the stacks comprise a rounded cross-sectional shape proximal to the pillar regions.

16 . The electronic structure of claim 1 , wherein the conductive materials of the stacks and the cell high-k dielectric material comprise a rounded cross-sectional shape proximal to the pillar regions.

17 . The electronic structure of claim 1 , wherein the conductive materials of the stacks exhibit a greater width proximal to the pillar high-k dielectric material than distal to the pillar high-k dielectric material.

18 . An electronic device comprising:
an array of memory cells, the memory cells comprising:
stacks of alternating dielectric materials and conductive materials in cell regions of the electronic device;
a pillar high-k dielectric material adjacent to and coextensive with the stacks and in pillar regions of the electronic device, the stacks disposed directly and continuously between the pillar regions, and the dielectric materials in the cell regions comprising rounded surfaces proximal to the pillar high-k dielectric material;
an etch stop material directly adjacent to and between the dielectric materials of the stacks and the pillar high-k dielectric material;
an interlayer poly-dielectric structure and a channel material adjacent to the pillar high-k dielectric material;
effective gate lengths of the conductive materials proximal the pillar regions being greater than gate lengths of the conductive materials distal from the pillar regions; and
a cell high-k dielectric material surrounding all surfaces of the conductive materials in the cell regions, and a portion of the cell high-k dielectric material adjoining a portion of the pillar high-k dielectric material in each of the pillar regions between which the stacks are directly and continuously disposed; and
access lines and bit lines electrically coupled to the memory cells.

19 . A system, comprising:
a processor operably coupled to an input device and an output device; and an electronic device operably coupled to the processor, the electronic device comprising memory cells, one or more of the memory cells comprising:
stacks of alternating dielectric materials and conductive materials in cell regions of the electronic device;
a pillar high-k dielectric material, an interlayer poly-dielectric structure, and a channel material adjacent to opposing sidewalls of the stacks and in pillar regions of the electronic device, the conductive materials in the cell region comprising a rounded cross-sectional shape proximal to the pillar high-k dielectric material;
an etch stop material directly adjacent to and between the dielectric materials of the stacks and the pillar high-k dielectric material;
a cell high-k dielectric material surrounding horizontal surfaces and vertical surfaces of the conductive materials in the cell regions and a portion of the cell high-k dielectric material adjoining a portion of the pillar high-k dielectric material adjacent and coextensive with each of the opposing sidewalls of the stacks; and
effective gate lengths of the conductive materials proximal the pillar regions being greater than gate lengths of the conductive materials

Assignees

• Micron Technology Inc

Inventors

• Surthi Shyam
• Carlson Chris M
• Hill Richard J
• Resnati Davide

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title