Wafer scale active thermal interposer for device testing

Patent metadata

Field	Value
Publication number	US-12540968-B2
Application number	US-202519201208-A
Country	US
Kind code	B2
Filing date	May 7, 2025
Priority date	Nov 19, 2020
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A system for testing circuits of an integrated circuit semiconductor wafer includes a thermal interposer (TI) device for use in testing circuits of a semiconductor device. The TI device includes a top surface configured to receive the semiconductor device, a heating layer defining a plurality of independently controllable thermal zones configured to maintain or change temperatures of the top surface during the testing, a power input configured to receive electrical power and wherein the electrical power is configured to be selectively applied to one or more of the plurality of independently controllable thermal zones, and an electromagnetic interference (EMI) shield layer defining the top surface and disposed to shield the top surface from EMI from the heating layer.

First claim

What is claimed is:

1 . A thermal interposer (TI) device for use in testing circuits of a semiconductor device, the TI device comprising:
a top surface configured to receive said semiconductor device; a heating layer defining a plurality of independently controllable thermal zones configured to maintain or change temperatures of the top surface during said testing; a power input configured to receive electrical power and wherein said electrical power is configured to be selectively applied to one or more of the plurality of independently controllable thermal zones; and an electromagnetic interference (EMI) shield layer defining said top surface and disposed to shield said top surface from EMI from said heating layer.

2 . The TI device as described in claim 1 wherein said EMI shield layer is configured to be coupled to ground and is further configured to shield said circuits of said semiconductor device from EMI from said heating layer.

3 . The TI device as described in claim 1 wherein said heating layer comprises a plurality of independently controllable heating elements which are configured to selectively provide heat for said plurality of independently controllable thermal zones.

4 . The TI device as described in claim 3 wherein said heating layer also comprises a plurality of temperature measurement elements disposed in proximity to said plurality of independently controllable heating elements.

5 . The TI device as described in claim 4 wherein said plurality of temperature measurement elements are configured to communicate with a thermal controller and wherein said plurality of independently controllable heating elements are configured to be driven under control of said thermal controller.

6 . The TI device as described in claim 3 wherein said semiconductor device comprises a plurality of discrete dice and wherein said plurality of independently controllable heating elements comprises a plurality of resistive traces configured to selectively emit heat responsive to selective application of said electrical power thereto and wherein said EMI shield layer is configured to protect said semiconductor device from EMI from said plurality of resistive traces.

7 . The TI device as described in claim 3 further comprising a bottom surface configured to receive a cold plate for selectively cooling one or more of said plurality of independently controllable thermal zones by selectively cooling said bottom surface which selectively cools one or more of said plurality of independently controllable heating elements of said heating layer.

8 . The TI device as described in claim 1 wherein said plurality of independently controllable thermal zones is configured as concentric rings, concentric arcs or sectors of thermal zones.

9 . The TI device as described in claim 1 wherein said plurality of independently controllable thermal zones is configured as rows of thermal zones, columns of thermal zones or a combination of both.

10 . The TI device as described in claim 1 wherein said top surface, said heating layer and said EMI shield layer are annular in shape.

11 . The TI device as described in claim 1 wherein the semiconductor device comprises at least one integrated circuit die device under test (DUT) and wherein a size of at least one of the plurality of independently controllable thermal zones is substantially the same or smaller as a size of the at least one integrated circuit die DUT.

12 . The TI device as described in claim 1 wherein the semiconductor device comprises at least one integrated circuit die device under test (DUT) and wherein an area of two or more of the plurality of independently controllable thermal zones is equal to or greater than an area of the at least one integrated circuit die DUT.

13 . The TI device as described in claim 1 wherein the electrical power is supplied by a high-power supply device configured to be coupled to said power input.

14 . The TI device as described in claim 13 wherein the electrical power is configured to be selectively applied to two or more of the plurality of independently controllable thermal zones.

15 . The TI device as described in claim 1 further comprising at least one vacuum passthrough channel configured to hold said semiconductor device in place with respect to said top surface.

16 . The TI device as described in claim 1 further comprising a bottom surface configured to receive a cold plate for selectively cooling one or more of said plurality of independently controllable thermal zones.

17 . The TI device as described in claim 1 further comprising a bottom surface configured to receive a cold plate for selectively cooling one or more of said plurality of independently controllable thermal zones by selectively cooling said bottom surface which selectively cools said one or more of said plurality of independently controllable thermal zones.

18 . A method of temperature control of a semiconductor device, the method comprising:
disposing said semiconductor device in proximity to a thermal interposer (TI) device; testing circuits of said semiconductor device based on probing thereof; and during said testing, controlling temperatures of said semiconductor device by selectively providing electrical power to said TI device, wherein said TI device comprises:
a top surface configured to receive said semiconductor device;
a heating layer defining a plurality of independently controllable thermal zones configured to maintain or change temperatures of the top surface during said testing;
a power input configured to receive said electrical power and wherein said electrical power is configured to be selectively applied to one or more of the plurality of independently controllable thermal zones; and
an electromagnetic interference (EMI) shield layer defining said top surface and disposed to shield said top surface from EMI from said heating layer.

19 . The method as described in claim 18 further comprising coupling said shield layer to ground.

20 . The method as described in claim 18 wherein said heating layer comprises a plurality of independently controllable heating elements and wherein said controlling temperatures comprises using said plurality of independently controllable heating elements to selectively provide heat for said plurality of independently controllable thermal zones.

21 . The method as described in claim 20 wherein said heating layer also comprises a plurality of temperature measurement elements disposed in proximity to said plurality of independently controllable heating elements and wherein said controlling temperatures further comprises:
communicating measurements from said plurality of temperature measurement elements to a thermal controller during said testing; and
driving said plurality of independently controllable heating elements under control of said thermal controller.

22 . The method as described in claim 18 wherein said plurality of independently controllable thermal zones is configured as concentric rings, concentric arcs or sectors of thermal zones.

23 . The method as described in claim 18 wherein said plurality of independently controllable thermal zones is configured as rows of thermal zones, columns of thermal zones or a combination of both.

24 . The method as described in claim 18 wherein said top surface, said heating layer and said EMI shield layer are annular in shape.

25 . Th

Assignees

• Advantest Test Solutions Inc

Inventors

• Kabbani Samer
• Ferrari Paul
• Hiroki Ikeda
• Toshiyuki Kiyokawa
• Cruzan Gregory
• Ranganathan Karthik

Classifications

• F28F2260/02

  having microchannels · CPC title

• H01L23/473

  Electricity · mapped topic

• G01R31/318511

  Wafer Test · CPC title

• G01R31/2887 Primary

  involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392) · CPC title

• H10W40/47

  by flowing liquids, e.g. forced water cooling · CPC title