Wafer scale active thermal interposer for device testing

Patent metadata

Field	Value
Publication number	US-12540967-B2
Application number	US-202519201163-A
Country	US
Kind code	B2
Filing date	May 7, 2025
Priority date	Nov 19, 2020
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A system for testing circuits of an integrated circuit semiconductor wafer includes a test stack for use in testing circuits of an integrated circuit component includes a top surface configured to receive the component in proximity thereto, a plurality of independently controllable thermal zones including a plurality of independently controllable heating zones and a plurality of independently controllable cooling zones configured to maintain or change temperatures on the top surface, and a power input configured to receive electrical power and wherein the electrical power is configured to be selectively applied to one or more of the plurality of independently controllable heating zones.

First claim

What is claimed is:

1 . A test stack for use in testing circuits of an integrated circuit component, the test stack comprising:
an active thermal interposer comprising:
a top surface configured to receive said integrated circuit component in proximity thereto;
a bottom surface configured to be placed upon a cold plate:
a plurality of independently controllable thermal zones comprising a plurality of independently controllable heating zones configured to maintain or change temperatures on the top surface; and
a plurality of healing elements, associated with said plurality of independently controllable heating zones, contained between said top and bottom surfaces;
a plurality of indepndently controllable cooling zones configured to maintain or change temperatures on the top surface; and a power input configured to receive electrical power and wherein said electrical power is configured to be selectively applied to one or more of the plurality of independently controllable heating zones.

2 . The test stack as described in claim 1 wherein the electrical power is supplied by a power supply device coupled to said power input and wherein said power supply device selectively applies said electrical power using pulse width modulation (PWM).

3 . The test stack as described in claim 1 wherein temperatures maintained or changed on said top surface are operable to cause maintaining or changing of temperatures of said component disposed in proximity to said top surface.

4 . The test stack as described in claim 3 wherein said component is a semiconductor wafer comprising a plurality of discrete dice and wherein further said plurality of discrete dice comprises at least one integrated circuit die device under test (DUT).

5 . The test stack as described in claim 4 further comprising a wafer thermal interposer (TI) having a top surface configured to be disposed adjacent to the semiconductor wafer and configured to be electrically coupled to ground.

6 . The test stack as described in claim 1 further comprising a wafer probe and wherein the wafer probe is configured to electrically couple to a device under test (DUT) of said component during testing thereof.

7 . The test stack as described in claim 1 further comprising a wafer thermal interposer (TI) comprising:
a first conductive layer comprising said plurality of independently controllable heating zones, wherein said plurality of independently controllable heating zones comprise one or more resistive traces configured as heat producing elements; and
a second conductive layer configured as an electromagnetic interference (EMI) shield layer, wherein the shield layer is located closer to said top surface than the first conductive layer and is electrically coupled to ground.

8 . The test stack as described in claim 7 wherein the first conductive layer of said wafer TI further comprises a plurality of heat sensing elements.

9 . The test stack as described in claim 7 wherein the wafer TI is formed from two or more substrates.

10 . The test stack described in claim 1 wherein said component is a wafer device under test (DUT) and further comprising:
a wafer probe configured to probe circuits of the wafer DUT by probing a first surface of said wafer DUT;
a wafer thermal interposer (TI) configured to be disposed in proximity to a second surface of said wafer DUT and further configured to selectively heat areas of said wafer DUT during testing thereof, said wafer TI comprising said plurality of independently controllable heating zones;
a cold plate configured to be disposed in proximity to said wafer TI and configured to selectively cool said wafer DUT; and
a thermal controller configured to control selective heating of said wafer TI and configured to control selective cooling of said cold plate.

11 . The test stack as described in claim 10 wherein said cold plate and said wafer TI, in combination, under control of said thermal controller, implement said plurality of independently controllable cooling zones.

12 . The test stack as described in claim 10 wherein said plurality of independently controllable heating zones comprises a plurality of resistive traces configured to emit heat responsive to application of said electrical power thereto.

13 . The test stack as described in claim 12 wherein said wafer TI further comprises a shield layer disposed to protect said wafer DUT from electromagnetic interference from said plurality of resistive traces and wherein said shield layer is configured to be grounded.

14 . The test stack as described in claim 10 wherein said thermal controller is configured to control electrical power selectively supplied to one or more of said plurality of independently controllable thermal zones to individually control heat produced therefrom.

15 . The test stack as described in claim 10 wherein said wafer TI further comprises a plurality of temperature measurement devices configured to measure temperatures of said areas of said wafer DUT.

16 . The test stack as described in claim 10 further comprising:
a first thermal interface material (TIM) layer disposed between said cold plate and said wafer TI; and
a second TIM layer disposed between said wafer TI and said wafer DUT.

17 . The test stack as described in claim 10 wherein said thermal controller is configured to alter a flow rate of coolant fluid to said cold plate.

18 . The test stack as described in claim 10 wherein said thermal controller is configured to alter a temperature of coolant fluid flowing to said cold plate.

19 . The test stack as described in claim 10 wherein said thermal controller is configured to alter and maintain temperature of a respective thermal zone of said plurality of independently controllable thermal zones by adjusting power supplied to said respective thermal zone and also by adjusting coolant fluid flow to said cold plate, or both.

20 . A method of testing an integrated circuit component, said method comprising:
testing said component by applying signals thereto and comparing results therefrom; and regulating temperatures of said integrated circuit component during said testing, said regulating temperatures using a test stack, wherein the test stack comprises: an active thermal interposer comprising:
a top surface configured to receive said integrated circuit component in proximity thereto;
a bottom surface nfigured to be placed upon a cold plate;
a plurality of independently controllable thermal zones comprising a plurality of independently controllable heating zones configured to maintain or change temperatures on the top surface; and
a plurality of heating elements, assocaited with said plurality of independently controllable heating zones, contained between said top and bottom surfaces;
a plurality of independently controllable cooling zones configured to maintain of change temperatures on the top surface: and a power input configured to receive electrical power and wherein said electrical power is configured to be selectively applied to one or more of the plurality of independently controllable heating zones.

21 . The method as described in claim 20 wherein said regulating temperatures comprises supplying the electrical power using a power supply device coupled to said power input and wherein further the supplying electrical power comprises selectively applying said electrical power using pulse width modulation (PWM).

22 . The method as described in claim 2

Assignees

• Advantest Test Solutions Inc

Inventors

• Kabbani Samer
• Ferrari Paul
• Hiroki Ikeda
• Toshiyuki Kiyokawa
• Cruzan Gregory
• Ranganathan Karthik

Classifications

• F28F2260/02

  having microchannels · CPC title

• H01L23/473

  Electricity · mapped topic

• G01R31/318511

  Wafer Test · CPC title

• G01R31/2887 Primary

  involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392) · CPC title

• H10W40/47

  by flowing liquids, e.g. forced water cooling · CPC title