Semiconductor structure having different heights of active regions

Patent metadata

Field	Value
Publication number	US-12538580-B2
Application number	US-202016858293-A
Country	US
Kind code	B2
Filing date	Apr 24, 2020
Priority date	Oct 30, 2019
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A semiconductor structure includes a first cell and a second cell. The second cell vertically abuts the first cell. Each first cell has a plurality of first active regions. Each first active region has a first vertical height. Each second cell has a plurality of second active regions. Each second active region has a second vertical height. The second vertical height is different from the first vertical height.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first cell having a first cell height, the first cell comprising:
a first boundary polysilicon section and a second boundary polysilicon section;
a first gate polysilicon section disposed between the first boundary polysilicon section and the second boundary polysilicon section, and the first gate polysilicon section separated from the first boundary polysilicon section and the second boundary polysilicon section; and
a plurality of first active regions separated from each other, the plurality of first active regions disposed between and connected to the first boundary polysilicon section and the first gate polysilicon section, the plurality of first active regions disposed between and connected to the second boundary polysilicon section and the first gate polysilicon section, each of the plurality of first active regions having a first vertical height;
a second cell vertically abutting the first cell and having a second cell height different from the first cell height, the second cell comprising:
a third boundary polysilicon section and a fourth boundary polysilicon section;
a second gate polysilicon section disposed between the third boundary polysilicon section and the fourth boundary polysilicon section, and the second gate polysilicon section separated from the third boundary polysilicon section and the fourth boundary polysilicon section; and
a plurality of second active regions separated from each other, the plurality of second active regions disposed between and connected to the third boundary polysilicon section and the second gate polysilicon section, the plurality of second active regions disposed between and connected to the fourth boundary polysilicon section and the second gate polysilicon section, each of the plurality of second active regions having a second vertical height;
a first track cell disposed above the first cell, the first track cell having a first amount of first tracks; and a second track cell disposed above the second cell, the second track cell having a second amount of first tracks, wherein the first amount is different from the second amount, wherein the second vertical height is different from the first vertical height, wherein the first boundary polysilicon section is connected to the third boundary polysilicon section to form a first boundary polysilicon segment extending from the first cell to the second cell, the second polysilicon section is connected to the fourth boundary polysilicon section to form a second boundary polysilicon segment extending from the first cell to the second cell, and the first gate polysilicon section is connected to the second gate polysilicon section to form a gate polysilicon segment extending from the first cell to the second cell.

2 . The semiconductor structure of claim 1 , further comprising a third cell vertically abutting the first cell or the second cell, a third active region of the third cell having a third vertical height, and the third vertical height being different from the first vertical height and the second vertical height.

3 . The semiconductor structure of claim 1 , wherein the first tracks in the first track cell and the second tracks in the second track cell are parallel to the first active regions and the second active regions, the first track cell and the second track cell are disposed on a metal-n layer.

4 . The semiconductor structure of claim 3 , further comprising a third track cell vertically abuts the first track cell or the second track cell, the third track cell having a third amount of third tracks, the third amount is different from the first amount and the second amount.

5 . The semiconductor structure of claim 1 , wherein the first cell and the second cell are formed as a cell group.

6 . The semiconductor structure of claim 1 , wherein a ratio of the first vertical height and the second vertical height is 3:1.

7 . The semiconductor structure of claim 6 , wherein a ratio of the first amount and the second amount is 3:2.

8 . The semiconductor structure of claim 6 , wherein the first amount is six and the second amount is four.

9 . The semiconductor structure of claim 1 , wherein a ratio of the first vertical height and the second vertical height is 2:3.

10 . The semiconductor structure of claim 9 , wherein a ratio of the first amount and the second amount is 5:6.

11 . A semiconductor structure, comprising:
a plurality of cell columns, each cell column having a plurality of first cells and a plurality of second cells, the second cell vertically abutting the first cell, wherein each of the plurality of first cells has a first cell height and each of the plurality of second cells has a second cell height different from the first cell height, each cell column comprising:
a first boundary polysilicon segment and a second boundary polysilicon segment extending along a first direction through the plurality of first cells and the plurality of second cells;
a gate polysilicon segment disposed between the first boundary polysilicon segment and the second boundary polysilicon segment, and the gate polysilicon segment separated from the first boundary polysilicon segment and the second boundary polysilicon segment, wherein the gate polysilicon segment along the first direction extends through the plurality of first cells and the plurality of second cells;
a plurality of first active regions disposed in the first cells and separated from each other, the plurality of first active regions disposed between and connected to the first boundary polysilicon segment and the gate polysilicon segment, and disposed between and connected to the second boundary polysilicon segment and the gate polysilicon segment, each first active region having a first vertical height; and
a plurality of second active regions disposed in the second cells and separated from each other, the plurality of second active regions disposed between and connected to the first boundary polysilicon segment and the gate polysilicon segment, and disposed between and connected to the second boundary polysilicon segment and the gate polysilicon segment, each second active region having a second vertical height different from the first vertical height; and
a plurality of track columns disposed above the cell columns, wherein each track column comprises a plurality of first track cells and a plurality of second track cells, wherein the first track cells are disposed above the first cells, and the second track cells are disposed above the second cells, wherein the first track cell has a plurality of first tracks, and the second track cell has a plurality of second tracks, and wherein a ratio of the number of the first tracks and the number of the second tracks is 4:5.

12 . The semiconductor structure of claim 11 , wherein the first cells vertically abut, and the second cells vertically abut, one of the second cells vertically abuts one of the first cells.

13 . The semiconductor structure of claim 11 , wherein the cell columns are aligned in a second direction substantially perpendicular to the first direction.

14 . The semiconductor structure of claim 11 , wherein the track columns are disposed on a metal-n layer.

15 . The semiconductor structure of claim 11 , wherein the track columns are aligned in a second direction substantially perpendicular to the first direction.

16 . The semiconductor structure of claim 11 , wherein the first vertical height is half of the second vertical height.

17 . A semiconductor structure, comprising:
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Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Jian-Sing
• Lu Chi-Yu
• Zhuang hui-zhong
• Chen Chih-Liang

Classifications

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D84/962

  Horizontal or vertical grid line density · CPC title

• H10D84/959

  Connectability characteristics, i.e. diffusion and polysilicon geometries · CPC title

• H10D84/907

  CMOS gate arrays · CPC title