Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12538540-B2
Application number	US-202217844746-A
Country	US
Kind code	B2
Filing date	Jun 21, 2022
Priority date	May 23, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

First claim

What is claimed is:

1 . A manufacturing method of a semiconductor device, comprising:
forming a III-V compound barrier layer on a III-V compound semiconductor layer; forming a silicon-rich tensile stress layer on the III-V compound barrier layer; and performing an annealing process after the silicon-rich tensile stress layer is formed, wherein a part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process, the silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer, the silicon-rich tensile stress layer comprises silicon carbide, and the silicon-doped III-V compound barrier layer is in direct physical contact with the III-V compound semiconductor layer and the silicon-rich tensile stress layer.

2 . The manufacturing method of the semiconductor device according to claim 1 , further comprising:
forming a passivation layer on the silicon-rich tensile stress layer after the annealing process.

3 . The manufacturing method of the semiconductor device according to claim 2 , wherein a tensile stress of the silicon-rich tensile stress layer is higher than a tensile stress of the passivation layer.

4 . The manufacturing method of the semiconductor device according to claim 2 , wherein a thickness of the passivation layer is greater than a thickness of the silicon-rich tensile stress layer.

5 . The manufacturing method of the semiconductor device according to claim 2 , further comprising:
forming an ultraviolet (UV)-transparent protection layer on the passivation layer.

6 . The manufacturing method of the semiconductor device according to claim 5 , wherein a tensile stress of the passivation layer is higher than a tensile stress of the UV-transparent protection layer.

7 . The manufacturing method of the semiconductor device according to claim 5 , further comprising:
performing an UV treatment after the UV-transparent protection layer is formed, wherein a tensile stress of the passivation layer is increased by the UV treatment.

8 . The manufacturing method of the semiconductor device according to claim 7 , further comprising:
forming a source structure and a drain structure, wherein the source structure and the drain structure penetrate through the UV-transparent protection layer, the passivation layer, and the silicon-rich tensile stress layer in a vertical direction.

9 . The manufacturing method of the semiconductor device according to claim 8 , wherein the source structure and the drain structure are formed after the UV-transparent protection layer is formed and before the UV treatment.

10 . The manufacturing method of the semiconductor device according to claim 7 , further comprising:
forming a gate structure penetrating through the UV-transparent protection layer, the passivation layer, and the silicon-rich tensile stress layer after the UV treatment.

Assignees

• United Microelectronics Corp

Inventors

• Lin da-jun
• Tsai Fu-Yu
• Tsai Bin-Siang
• Chiu Chung-Yi

Classifications

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D30/015 Primary

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D62/8503 Primary

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title