Method for manufacturing a semiconductor structure having a passivated III-nitride layer

Patent metadata

Field	Value
Publication number	US-9761438-B1
Application number	US-201414272993-A
Country	US
Kind code	B1
Filing date	May 8, 2014
Priority date	May 8, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor structure; the method comprising:
forming a layer of a III-N material;
covering at least a portion of said III-N material layer with a first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure; and
covering the first layer of SiN with a second layer of SiN; the second SiN layer having a second thickness and generating compressive stress in the structure; comprising forming the first SiN layer with a H content lower than 5% and the second SiN layer with a H content greater than 5%;
the method further comprising forming the first SiN layer at a temperature higher than 600 degree C. and forming the second SiN layer at a temperature lower than 400 degree C.

2. The method of claim 1 , wherein the III-N material is AlGaN.

3. The method of claim 1 , comprising:
forming the first SiN layer with 44.2% of Si, 54.7% of N, 0.6% of H and 0.5% of Cl; and
forming the second SiN layer with 43.5% of Si, 33.5% of N and 23% of H.

4. The method of claim 1 , comprising forming the first SiN layer with a thickness of 2-50 nm and the second SiN layer with a thickness of 50-200 nm.

5. The method of claim 2 , wherein the layer of a III-N material is formed on an AlN spacer layer on a GaN channel layer.

6. The method of claim 1 , further comprising forming a transistor using the III-N material layer as a barrier layer;
said forming a transistor including:
filling recesses passing through said first and second SiN layers and said barrier layer with a source Ohmic contact electrode and a drain Ohmic contact electrode both contacting a channel layer below said barrier layer; and
forming a gate trench through the passivation layer with a bottom of the trench contacting said III-N material layer, and forming an insulating layer over the bottom of the gate trench, over the walls of the gate trench and over the second SiN layer and in contact with the source Ohmic contact electrode and the drain Ohmic contact electrode.

Assignees

• Hrl Lab Llc

Inventors

• Chu Rongming
• Chen Xu

Classifications

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• H10P14/69433 Primary

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title