Semiconductor package including SoIC die stacks

Patent metadata

Field	Value
Publication number	US-12532776-B2
Application number	US-202217714147-A
Country	US
Kind code	B2
Filing date	Apr 6, 2022
Priority date	Apr 6, 2022
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A semiconductor package is provided. The semiconductor package includes: an interposer; a System on Integrated Chips (SoIC) die stack bonded to a top surface of the interposer, the SoIC die stack comprising two or more dies bonded together; and a plurality of chips bonded to the top surface of the interposer. A first lateral distance, in a first direction, between a first boundary of the SoIC die stack and a boundary of a neighboring chip among the plurality of chips is larger than a first threshold distance.

First claim

What is claimed is:

1 . A semiconductor package comprising:
an interposer; a System on Integrated Chips (SoIC) die stack bonded to a top surface of the interposer, the SoIC die stack comprising two or more dies bonded together; and a plurality of chips bonded to the top surface of the interposer; and wherein a first lateral distance, in a first direction, between a first boundary of the SoIC die stack and a boundary of a neighboring chip among the plurality of chips is larger than a first threshold distance; wherein a second lateral distance, in the first direction, between a second boundary of the SoIC die stack and a boundary of the interposer is larger than a second threshold distance.

2 . The semiconductor package of claim 1 further comprising:
a first package substrate, wherein the interposer is bonded to a top surface of the first package substrate, and wherein a third lateral distance, in the first direction, between the second boundary of the SoIC die stack and a boundary of the first package substrate is larger than a third threshold distance.

3 . The semiconductor package of claim 2 further comprising:
a second package substrate, wherein the first package substrate is bonded to a top surface of the second package substrate, and wherein a fourth lateral distance, in the first direction, between the second boundary of the SoIC die stack and a boundary of the second package substrate is larger than the third lateral distance.

4 . The semiconductor package of claim 2 , wherein the third threshold distance is 80 μm.

5 . The semiconductor package of claim 1 , wherein the two or more dies are bonded together using hybrid bonding.

6 . The semiconductor package of claim 1 , wherein the two or more dies are bonded together using fusion bonding.

7 . The semiconductor package of claim 1 , wherein the SoIC die stack is bonded to the interposer using hybrid bonding.

8 . The semiconductor package of claim 1 , wherein the SoIC die stack is bonded to the interposer using fusion bonding.

9 . The semiconductor package of claim 1 , wherein the plurality of chips are bonded to the interposer using micro-bumps.

10 . The semiconductor package of claim 1 , wherein the first threshold distance is 30 μm.

11 . The semiconductor package of claim 1 , wherein the second threshold distance is 50 μm.

12 . The semiconductor package of claim 1 , wherein the neighboring chip is one of a logic chip, a memory chip, a computation chip, a sensor chip, a radio frequency (RF) chip, or a high voltage (HV) chip.

13 . The semiconductor package of claim 1 , wherein the SoIC die stack comprises a top die, a middle die, and a bottom die bonded together.

14 . The semiconductor package of claim 1 , wherein at least one die in the SoIC die stack comprises a seal ring configured to prevent intrusion of cracks and moisture.

15 . A semiconductor package comprising:
a first base structure; a die stack bonded to a top surface of the first base structure, the die stack comprising two or more dies bonded together using fusion bonding or hybrid bonding; and a plurality of chips bonded to the top surface of the first base structure; and wherein a first lateral distance, in a first direction, between a first boundary of the die stack and a boundary of a neighboring chip among the plurality of chips is larger than a first threshold distance; wherein a second lateral distance, in the first direction, between a second boundary of the die stack and a boundary of the first base structure is larger than a second threshold distance.

16 . The semiconductor package of claim 15 further comprising:
a second base structure, wherein the first base structure is bonded to a top surface of the second base structure, and wherein a third lateral distance, in the first direction, between the second boundary of the die stack and a boundary of the second base structure is larger than a third threshold distance.

17 . The semiconductor package of claim 16 further comprising:
a third base structure, wherein the second base structure is bonded to a top surface of the third base structure, and wherein a fourth lateral distance, in the first direction, between the second boundary of the die stack and a boundary of the third base structure is larger than the third lateral distance.

18 . The semiconductor package of claim 15 , wherein the first base structure is an interposer.

19 . A semiconductor package comprising:
an interposer; a System on Integrated Chips (SoIC) die stack bonded to a top surface of the interposer, the SoIC die stack comprising two or more dies bonded together; and a plurality of chips bonded to the top surface of the interposer, the plurality of chips comprising a first chip, the first chip being a neighboring chip of the SoIC die stack, wherein a first lateral distance, in a first horizontal direction, between a first boundary of the SoIC die stack and a boundary of the first chip is larger than a first threshold distance; wherein a second lateral distance, in the first horizontal direction, between a second boundary of the SoIC die stack and a boundary of the interposer is larger than a second threshold distance, the second boundary of the SoIC die stack being opposite to the first boundary of the SoIC die stack.

20 . A semiconductor package of claim 19 , wherein the first threshold distance is 30 μm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Jen-Yuan

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title