Porous mesh structures for the thermal management of integrated circuit devices

Patent metadata

Field	Value
Publication number	US-12532740-B2
Application number	US-202217709064-A
Country	US
Kind code	B2
Filing date	Mar 30, 2022
Priority date	Mar 30, 2022
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A porous mesh structure for use in the thermal management of integrated circuit devices may be formed as a solid matrix with a plurality of pores dispersed therein, wherein the solid matrix may be a plurality of fused matrix material particles and the plurality of pores may comprise between about 10% and 90% of a volume of the porous mesh structure. The porous mesh structure may be formed on an integrated circuit device and/or on a heat dissipation assembly component, and may be incorporated into an immersion cooling assembly, wherein the porous mesh structure may act as a nucleation site for a working fluid in the immersion cooling assembly.

First claim

What is claimed is:

1 . An apparatus, comprising:
a substrate comprising an integrated circuit (IC) device on a first side of the substrate; and a porous mesh structure on a second, opposite, side of the substrate, the porous mesh structure including:
a solid matrix comprising a lamellar structure of fused matrix material particles flattened to have a largest dimension non-orthogonal to the second side of the substrate; and
a plurality of pores dispersed in the solid matrix, wherein the plurality of pores comprises between about 10% and 90% of a volume of the porous mesh structure.

2 . The apparatus of claim 1 , wherein the solid matrix comprises a material selected from the group consisting of copper, aluminum, nickel, carbon, silicon carbide, and aluminum nitride.

3 . The apparatus of claim 1 , wherein the pores are layered within the lamellar structure of the fused matrix material particles, and wherein the pores are flattened to have a largest dimension non-orthogonal to the second side of the substrate.

4 . The apparatus of claim 3 , wherein the solid matrix comprises a plurality of voids, and wherein the plurality of voids comprises no more than 2% of the volume of the solid matrix.

5 . The apparatus of claim 3 , wherein the pores have an average diameter of between 10 and 500 microns.

6 . The apparatus of claim 3 , further comprising an intermediate layer between the substrate and the porous mesh structure, wherein the intermediate layer has a thickness of no more than 500 nm.

7 . The apparatus of claim 6 , wherein the intermediate layer is selected from the group consisting of titanium, nickel, vanadium, gold, and nitride compounds.

8 . A method, comprising:
receiving a substrate comprising an integrated circuit device on a first side of the substrate; depositing, with a cold-spray process, matrix material particles and sacrificial material particles on a second, opposite, side of the substrate, wherein the depositing forms a lamellar structure of fused matrix and sacrificial material particles that are flattened to have a largest dimension non-orthogonal to the second side of the substrate; and removing the sacrificial material particles to form a porous mesh structure of the fused matrix material particles, wherein the removal of the sacrificial material particles forms a plurality of pores that are flattened to have a largest dimension non-orthogonal to the second side of the substrate, wherein the plurality of pores comprises between about 10% and 90% of a volume of the porous mesh structure.

9 . The method of claim 8 , wherein depositing the matrix material particles comprises cold spraying a powder material selected from the group consisting of copper, aluminum, nickel, carbon, silicon carbide, and aluminum nitride at a temperature of no more than 150 degrees Celsius.

10 . The method of claim 8 , wherein depositing the matrix material particles and sacrificial material particles forms a plurality of voids within the lamellar structure, and wherein the plurality of voids comprises no more than 2% of the volume of the lamellar structure.

11 . The method of claim 8 , wherein forming the substrate comprises forming a heat dissipation device.

12 . The method of claim 8 , further comprising depositing an intermediate layer on the substrate before depositing the matrix material particles and sacrificial material particles.

13 . The method of claim 12 , wherein depositing the intermediate layer comprises forming, to a thickness of less than 500 nm, the intermediate layer from the group consisting of titanium, nickel, vanadium, gold, and nitride compounds.

14 . A system, comprising:
a board substrate; a plurality of integrated circuit devices electrically coupled to the board substrate; an epoxy mold compound between adjacent edges of the integrated circuit devices; and a porous mesh structure over a back side of the plurality of integrated circuit devices, wherein the porous mesh structure spans the epoxy mold compound, and comprises a solid matrix with a lamellar structure of fused matrix material particles flattened to have a largest dimension non-orthogonal to the back side of the integrated circuit devices and a plurality of pores dispersed in the solid matrix, and wherein the plurality of pores comprises between about 10% and 90% of a volume of the porous mesh structure.

15 . The system of claim 14 , wherein the solid matrix comprises a material selected from the group consisting of copper, aluminum, nickel, carbon, silicon carbide, and aluminum nitride.

16 . The system of claim 14 , wherein the pores are layered within the lamellar structure of the fused matrix material particles, and wherein the pores are flattened to have a largest dimension non-orthogonal to the back side of the substrate.

17 . The system of claim 14 , wherein the solid matrix comprises a plurality of voids, and wherein the plurality of voids comprises no more than 2% of the volume of the solid matrix.

18 . The system of claim 14 , further comprising an intermediate layer between the porous mesh structure and both of the epoxy mold compound and the back side of the plurality of integrated circuit devices.

19 . The system of claim 18 , wherein the intermediate layer has a thickness of no more than 500 nm and is selected from the group consisting of titanium, nickel, vanadium, gold, and nitride compounds.

20 . The system of claim 14 , further comprising a working fluid in contact with the porous mesh structure.

Assignees

• Intel Corp

Inventors

• Eid Feras
• Li Wenhao
• Diglio Paul
• Brun Xavier
• Swan Johanna

Classifications

• H10W70/02

  of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W40/30

  wherein the packaged device is completely immersed in a fluid other than air, e.g. immersed in a cryogenic fluid · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

• H10W40/25

  characterised by their materials · CPC title

• H10W40/259

  Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title